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Searched refs:cmdq_base (Results 1 – 14 of 14) sorted by relevance

/linux/drivers/infiniband/hw/bnxt_re/
H A Dqplib_tlv.h51 return ((struct cmdq_base *)GET_TLV_DATA(req))->opcode; in __get_cmdq_base_opcode()
60 ((struct cmdq_base *)GET_TLV_DATA(req))->opcode = val; in __set_cmdq_base_opcode()
68 return ((struct cmdq_base *)GET_TLV_DATA(req))->cookie; in __get_cmdq_base_cookie()
77 ((struct cmdq_base *)GET_TLV_DATA(req))->cookie = val; in __set_cmdq_base_cookie()
85 return ((struct cmdq_base *)GET_TLV_DATA(req))->resp_addr; in __get_cmdq_base_resp_addr()
94 ((struct cmdq_base *)GET_TLV_DATA(req))->resp_addr = val; in __set_cmdq_base_resp_addr()
102 return ((struct cmdq_base *)GET_TLV_DATA(req))->resp_size; in __get_cmdq_base_resp_size()
111 ((struct cmdq_base *)GET_TLV_DATA(req))->resp_size = val; in __set_cmdq_base_resp_size()
128 ((struct cmdq_base *)GET_TLV_DATA(req))->cmd_size = val; in __set_cmdq_base_cmd_size()
136 return ((struct cmdq_base *)GET_TLV_DATA(req))->flags; in __get_cmdq_base_flags()
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H A Dqplib_rcfw.h63 static inline void bnxt_qplib_rcfw_cmd_prep(struct cmdq_base *req, in bnxt_qplib_rcfw_cmd_prep()
97 static inline u32 bnxt_qplib_get_cmd_slots(struct cmdq_base *req) in bnxt_qplib_get_cmd_slots()
113 static inline u32 bnxt_qplib_set_cmd_slots(struct cmdq_base *req) in bnxt_qplib_set_cmd_slots()
240 struct cmdq_base *req;
H A Dqplib_sp.c77 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, in bnxt_qplib_query_version()
105 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, in bnxt_qplib_get_dev_attr()
203 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, in bnxt_qplib_set_func_resources()
272 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, in bnxt_qplib_del_sgid()
341 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, in bnxt_qplib_add_sgid()
404 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, in bnxt_qplib_update_sgid()
443 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, in bnxt_qplib_create_ah()
488 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, in bnxt_qplib_destroy_ah()
514 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, in bnxt_qplib_free_mrw()
549 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, in bnxt_qplib_alloc_mrw()
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H A Dqplib_rcfw.c457 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, in __destroy_timedout_ah()
461 msg.req = (struct cmdq_base *)&req; in __destroy_timedout_ah()
815 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, in bnxt_qplib_deinit_rcfw()
837 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, in bnxt_qplib_init_rcfw()
H A Dqplib_fp.c626 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, in bnxt_qplib_destroy_srq()
669 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, in bnxt_qplib_create_srq()
747 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, in bnxt_qplib_query_srq()
858 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, in bnxt_qplib_create_qp1()
1006 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, in bnxt_qplib_create_qp()
1295 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, in bnxt_qplib_modify_qp()
1409 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, in bnxt_qplib_query_qp()
1541 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, in bnxt_qplib_destroy_qp()
2173 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, in bnxt_qplib_create_cq()
2240 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, in bnxt_qplib_resize_cq()
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H A Droce_hsi.h104 struct cmdq_base { struct
/linux/drivers/gpu/drm/mediatek/
H A Dmtk_ethdr.c73 struct cmdq_client_reg cmdq_base; member
228 mtk_ddp_write(cmdq_pkt, HDR_VDO_FE_0804_BYPASS_ALL, &vdo_fe0->cmdq_base, in mtk_ethdr_config()
231 mtk_ddp_write(cmdq_pkt, HDR_VDO_FE_0804_BYPASS_ALL, &vdo_fe1->cmdq_base, in mtk_ethdr_config()
234 mtk_ddp_write(cmdq_pkt, HDR_GFX_FE_0204_BYPASS_ALL, &gfx_fe0->cmdq_base, in mtk_ethdr_config()
237 mtk_ddp_write(cmdq_pkt, HDR_GFX_FE_0204_BYPASS_ALL, &gfx_fe1->cmdq_base, in mtk_ethdr_config()
240 mtk_ddp_write(cmdq_pkt, HDR_VDO_BE_0204_BYPASS_ALL, &vdo_be->cmdq_base, in mtk_ethdr_config()
247 mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs, in mtk_ethdr_config()
249 mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs, in mtk_ethdr_config()
257 &mixer->cmdq_base, mixer->regs, MIX_DATAPATH_CON); in mtk_ethdr_config()
258 mtk_ddp_write_mask(cmdq_pkt, MIX_SRC_L0_EN, &mixer->cmdq_base, mixer->regs, in mtk_ethdr_config()
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/linux/tools/testing/selftests/kvm/lib/aarch64/
H A Dgic_v3_its.c168 static void its_send_cmd(void *cmdq_base, struct its_cmd_block *cmd) in its_send_cmd() argument
171 struct its_cmd_block *dst = cmdq_base + cwriter; in its_send_cmd()
200 void its_send_mapd_cmd(void *cmdq_base, u32 device_id, vm_paddr_t itt_base, in its_send_mapd_cmd() argument
211 its_send_cmd(cmdq_base, &cmd); in its_send_mapd_cmd()
214 void its_send_mapc_cmd(void *cmdq_base, u32 vcpu_id, u32 collection_id, bool valid) in its_send_mapc_cmd() argument
223 its_send_cmd(cmdq_base, &cmd); in its_send_mapc_cmd()
226 void its_send_mapti_cmd(void *cmdq_base, u32 device_id, u32 event_id, in its_send_mapti_cmd() argument
237 its_send_cmd(cmdq_base, &cmd); in its_send_mapti_cmd()
240 void its_send_invall_cmd(void *cmdq_base, u32 collection_id) in its_send_invall_cmd() argument
247 its_send_cmd(cmdq_base, &cmd); in its_send_invall_cmd()
/linux/tools/testing/selftests/kvm/include/aarch64/
H A Dgic_v3_its.h12 void its_send_mapd_cmd(void *cmdq_base, u32 device_id, vm_paddr_t itt_base,
14 void its_send_mapc_cmd(void *cmdq_base, u32 vcpu_id, u32 collection_id, bool valid);
15 void its_send_mapti_cmd(void *cmdq_base, u32 device_id, u32 event_id,
17 void its_send_invall_cmd(void *cmdq_base, u32 collection_id);
/linux/tools/testing/selftests/kvm/aarch64/
H A Dvgic_lpi_stress.c40 vm_paddr_t cmdq_base; member
117 test_data.cmdq_base, SZ_64K); in guest_setup_gic()
186 vm_paddr_t cmdq_base; in setup_test_data() local
196 cmdq_base = vm_phy_pages_alloc(vm, pages_per_64k, gpa_base, in setup_test_data()
198 virt_map(vm, cmdq_base, cmdq_base, pages_per_64k); in setup_test_data()
199 test_data.cmdq_base = cmdq_base; in setup_test_data()
200 test_data.cmdq_base_va = (void *)cmdq_base; in setup_test_data()
/linux/drivers/accel/ivpu/
H A Divpu_jsm_msg.h27 u32 pid, u32 engine, u64 cmdq_base, u32 cmdq_size);
30 u64 cmdq_base, u32 cmdq_size);
H A Divpu_jsm_msg.c283 u32 pid, u32 engine, u64 cmdq_base, u32 cmdq_size) in ivpu_jsm_hws_create_cmdq() argument
294 req.payload.hws_create_cmdq.cmdq_base = cmdq_base; in ivpu_jsm_hws_create_cmdq()
323 u64 cmdq_base, u32 cmdq_size) in ivpu_jsm_hws_register_db() argument
332 req.payload.hws_register_db.cmdq_base = cmdq_base; in ivpu_jsm_hws_register_db()
H A Dvpu_jsm_api.h754 u64 cmdq_base; member
830 u64 cmdq_base; member
/linux/drivers/soc/mediatek/
H A Dmtk-mmsys.c160 struct cmdq_client_reg cmdq_base; member
169 if (mmsys->cmdq_base.size && cmdq_pkt) { in mtk_mmsys_update_bits()
170 ret = cmdq_pkt_write_mask(cmdq_pkt, mmsys->cmdq_base.subsys, in mtk_mmsys_update_bits()
171 mmsys->cmdq_base.offset + offset, val, in mtk_mmsys_update_bits()
423 ret = cmdq_dev_get_client_reg(dev, &mmsys->cmdq_base, 0); in mtk_mmsys_probe()