| /linux/arch/mips/kernel/ |
| H A D | perf_event_mipsxx.c | 60 unsigned int cntr_mask; member
318 unsigned long cntr_mask; in mipsxx_pmu_alloc_counter() local
753 if (pev->cntr_mask == 0) in mipspmu_map_cache_event()
1716 raw_event.cntr_mask = in mipsxx_pmu_map_raw_event()
1730 raw_event.cntr_mask = in mipsxx_pmu_map_raw_event()
1746 raw_event.cntr_mask = in mipsxx_pmu_map_raw_event()
1756 raw_event.cntr_mask = in mipsxx_pmu_map_raw_event()
1770 raw_event.cntr_mask = in mipsxx_pmu_map_raw_event()
1786 raw_event.cntr_mask = in mipsxx_pmu_map_raw_event()
1801 raw_event.cntr_mask = in mipsxx_pmu_map_raw_event()
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| /linux/arch/x86/events/ |
| H A D | core.c | 196 u64 cntr_mask = x86_pmu.cntr_mask64; in get_possible_counter_mask() local
200 return cntr_mask; in get_possible_counter_mask()
203 cntr_mask |= x86_pmu.hybrid_pmu[i].cntr_mask64; in get_possible_counter_mask()
205 return cntr_mask; in get_possible_counter_mask()
210 u64 cntr_mask = get_possible_counter_mask(); in reserve_pmc_hardware() local
227 for_each_set_bit(i, (unsigned long *)&cntr_mask, end) in reserve_pmc_hardware()
241 u64 cntr_mask = get_possible_counter_mask(); in release_pmc_hardware() local
269 for_each_set_bit(i, cntr_mask, X86_PMC_IDX_MAX) { in check_hw_exists()
1525 unsigned long *cntr_mask, *fixed_cntr_mask; in perf_event_print_debug() local
1535 cntr_mask = hybrid(cpuc->pmu, cntr_mask); in perf_event_print_debug()
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| H A D | perf_event.h | 701 unsigned long cntr_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; member
798 unsigned long cntr_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; member
1159 bool check_hw_exists(struct pmu *pmu, unsigned long *cntr_mask,
1725 static inline u64 intel_pmu_pebs_mask(u64 cntr_mask) in intel_pmu_pebs_mask() argument
1727 return MAX_PEBS_EVENTS_MASK & cntr_mask; in intel_pmu_pebs_mask()
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| /linux/drivers/perf/ |
| H A D | arm_xscale_pmu.c | 173 for_each_set_bit(idx, cpu_pmu->cntr_mask, XSCALE1_NUM_COUNTERS) { in xscale1pmu_handle_irq()
370 bitmap_set(cpu_pmu->cntr_mask, 0, XSCALE1_NUM_COUNTERS); in xscale1pmu_init()
506 for_each_set_bit(idx, cpu_pmu->cntr_mask, XSCALE2_NUM_COUNTERS) { in xscale2pmu_handle_irq()
726 bitmap_set(cpu_pmu->cntr_mask, 0, XSCALE2_NUM_COUNTERS); in xscale2pmu_init()
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| H A D | arm_pmuv3.c | 774 for_each_andnot_bit(i, cpu_pmu->cntr_mask, cpuc->used_mask, in armv8pmu_enable_user_access()
860 for_each_set_bit(idx, cpu_pmu->cntr_mask, ARMPMU_MAX_HWEVENTS) { in armv8pmu_handle_irq()
899 for_each_set_bit(idx, cpu_pmu->cntr_mask, ARMV8_PMU_MAX_GENERAL_COUNTERS) { in armv8pmu_get_single_idx()
915 for_each_set_bit(idx, cpu_pmu->cntr_mask, ARMV8_PMU_MAX_GENERAL_COUNTERS) { in armv8pmu_get_chain_idx()
954 test_bit(ARMV8_PMU_INSTR_IDX, cpu_pmu->cntr_mask) && in armv8pmu_get_event_idx()
1061 bitmap_to_arr64(&mask, cpu_pmu->cntr_mask, ARMPMU_MAX_HWEVENTS); in armv8pmu_reset()
1211 bitmap_set(cpu_pmu->cntr_mask, in __armv8pmu_probe_pmu()
1215 set_bit(ARMV8_PMU_CYCLE_IDX, cpu_pmu->cntr_mask); in __armv8pmu_probe_pmu()
1219 set_bit(ARMV8_PMU_INSTR_IDX, cpu_pmu->cntr_mask); in __armv8pmu_probe_pmu()
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| H A D | arm_v7_pmu.c | 716 return test_bit(idx, cpu_pmu->cntr_mask); in armv7_pmnc_counter_valid()
838 for_each_set_bit(cnt, cpu_pmu->cntr_mask, ARMV7_IDX_COUNTER_MAX) { in armv7_pmnc_dump_regs()
940 for_each_set_bit(idx, cpu_pmu->cntr_mask, ARMPMU_MAX_HWEVENTS) { in armv7pmu_handle_irq()
1009 for_each_set_bit(idx, cpu_pmu->cntr_mask, ARMV7_IDX_COUNTER_MAX) { in armv7pmu_get_event_idx()
1064 for_each_set_bit(idx, cpu_pmu->cntr_mask, ARMPMU_MAX_HWEVENTS) { in armv7pmu_reset()
1148 bitmap_set(cpu_pmu->cntr_mask, 0, nb_cnt); in armv7_read_num_pmnc_events()
1151 set_bit(ARMV7_IDX_CYCLE_COUNTER, cpu_pmu->cntr_mask); in armv7_read_num_pmnc_events()
1522 for_each_set_bit(idx, cpu_pmu->cntr_mask, ARMV7_IDX_COUNTER_MAX) { in krait_pmu_reset()
1546 bit += bitmap_weight(cpu_pmu->cntr_mask, ARMV7_IDX_COUNTER_MAX); in krait_event_to_bit()
1844 for_each_set_bit(idx, cpu_pmu->cntr_mask, ARMV7_IDX_COUNTER_MAX) { in scorpion_pmu_reset()
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| H A D | arm_v6_pmu.c | 258 for_each_set_bit(idx, cpu_pmu->cntr_mask, ARMV6_NUM_COUNTERS) { in armv6pmu_handle_irq()
396 bitmap_set(cpu_pmu->cntr_mask, 0, ARMV6_NUM_COUNTERS); in armv6pmu_init()
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| H A D | arm_pmu.c | 745 for_each_set_bit(idx, armpmu->cntr_mask, ARMPMU_MAX_HWEVENTS) { in cpu_pm_pmu_setup()
928 pmu->name, bitmap_weight(pmu->cntr_mask, ARMPMU_MAX_HWEVENTS), in armpmu_register()
929 ARMPMU_MAX_HWEVENTS, &pmu->cntr_mask, in armpmu_register()
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| H A D | apple_m1_cpu_pmu.c | 435 for_each_set_bit(idx, cpu_pmu->cntr_mask, M1_PMU_NR_COUNTERS) { in m1_pmu_handle_irq()
595 bitmap_set(cpu_pmu->cntr_mask, 0, M1_PMU_NR_COUNTERS); in m1_pmu_init()
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| /linux/arch/x86/events/amd/ |
| H A D | core.c | 435 for_each_set_bit(i, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) { in __amd_put_nb_event_constraints()
547 for_each_set_bit(i, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) { in amd_alloc_nb()
740 for_each_set_bit(idx, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) { in amd_pmu_check_overflow()
760 for_each_set_bit(idx, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) { in amd_pmu_enable_all()
983 for_each_set_bit(idx, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) { in amd_pmu_v2_handle_irq()
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| /linux/include/linux/perf/ |
| H A D | arm_pmu.h | 103 DECLARE_BITMAP(cntr_mask, ARMPMU_MAX_HWEVENTS);
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| /linux/arch/x86/events/intel/ |
| H A D | p4.c | 922 for_each_set_bit(idx, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) { in p4_pmu_disable_all()
1001 for_each_set_bit(idx, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) { in p4_pmu_enable_all()
1043 for_each_set_bit(idx, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) { in p4_pmu_handle_irq()
1398 for_each_set_bit(i, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) { in p4_pmu_init()
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| H A D | core.c | 2937 unsigned long *cntr_mask = hybrid(cpuc->pmu, cntr_mask); in intel_pmu_reset() local
2942 if (!*(u64 *)cntr_mask) in intel_pmu_reset()
2949 for_each_set_bit(idx, cntr_mask, INTEL_PMC_MAX_GENERIC) { in intel_pmu_reset()
4265 for_each_set_bit(idx, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) { in core_guest_get_msrs()
4815 static void intel_pmu_check_counters_mask(u64 *cntr_mask, in intel_pmu_check_counters_mask() argument
4821 bit = fls64(*cntr_mask); in intel_pmu_check_counters_mask()
4825 *cntr_mask &= GENMASK_ULL(INTEL_PMC_MAX_GENERIC - 1, 0); in intel_pmu_check_counters_mask()
4827 *intel_ctrl = *cntr_mask; in intel_pmu_check_counters_mask()
4840 u64 cntr_mask,
6170 u64 cntr_mask, in intel_pmu_check_event_constraints() argument
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| /linux/arch/arm64/kvm/ |
| H A D | pmu-emul.c | 916 return bitmap_weight(arm_pmu->cntr_mask, ARMV8_PMU_MAX_GENERAL_COUNTERS); in kvm_arm_pmu_get_max_counters()
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