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Searched refs:csrows (Results 1 – 24 of 24) sorted by relevance

/linux/drivers/edac/
H A Dedac_mc.c128 mci->nr_csrows, mci->csrows); in edac_mc_dump_mci()
190 if (mci->csrows) { in mci_release()
192 csr = mci->csrows[row]; in mci_release()
203 kfree(mci->csrows); in mci_release()
219 mci->csrows = kcalloc(tot_csrows, sizeof(*mci->csrows), GFP_KERNEL); in edac_mc_alloc_csrows()
220 if (!mci->csrows) in edac_mc_alloc_csrows()
230 mci->csrows[row] = csr; in edac_mc_alloc_csrows()
756 struct csrow_info **csrows = mci->csrows; in edac_mc_find_csrow_by_page() local
763 struct csrow_info *csrow = csrows[i]; in edac_mc_find_csrow_by_page()
910 mci->csrows[row]->ce_count += count; in edac_inc_csrow()
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H A Damd76x_edac.c148 mci->csrows[row]->first_page, 0, 0, in amd76x_process_error_info()
163 mci->csrows[row]->first_page, 0, 0, in amd76x_process_error_info()
195 csrow = mci->csrows[index]; in amd76x_init_csrows()
H A Dpasemi_edac.c102 mci->csrows[cs]->first_page, 0, 0, in pasemi_edac_process_error_info()
109 mci->csrows[cs]->first_page, 0, 0, in pasemi_edac_process_error_info()
132 csrow = mci->csrows[index]; in pasemi_edac_init_csrows()
H A Dedac_mc_sysfs.c459 csrow = mci->csrows[i]; in edac_create_csrow_objects()
462 err = edac_create_csrow_object(mci, mci->csrows[i], i); in edac_create_csrow_objects()
470 if (device_is_registered(&mci->csrows[i]->dev)) in edac_create_csrow_objects()
471 device_unregister(&mci->csrows[i]->dev); in edac_create_csrow_objects()
482 if (device_is_registered(&mci->csrows[i]->dev)) in edac_delete_csrow_objects()
483 device_unregister(&mci->csrows[i]->dev); in edac_delete_csrow_objects()
696 struct csrow_info *ri = mci->csrows[row]; in mci_reset_counters_store()
826 struct csrow_info *csrow = mci->csrows[csrow_idx]; in mci_size_mb_show()
H A Dcell_edac.c37 struct csrow_info *csrow = mci->csrows[0]; in cell_edac_count_ce()
60 struct csrow_info *csrow = mci->csrows[0]; in cell_edac_count_ue()
130 struct csrow_info *csrow = mci->csrows[0]; in cell_edac_init_csrows()
H A Di82975x_edac.c310 chan = (mci->csrows[row]->nr_channels == 1) ? 0 : info->eap & 1; in i82975x_process_error_info()
313 (1 << mci->csrows[row]->channels[chan]->dimm->grain)); in i82975x_process_error_info()
382 csrow = mci->csrows[index]; in i82975x_init_csrows()
407 dimm = mci->csrows[index]->channels[chan]->dimm; in i82975x_init_csrows()
H A Daspeed_edac.c94 struct csrow_info *csrow = mci->csrows[0]; in count_rec()
127 struct csrow_info *csrow = mci->csrows[0]; in count_un_rec()
233 struct csrow_info *csrow = mci->csrows[0]; in init_csrows()
H A Di82860_edac.c118 dimm = mci->csrows[row]->channels[0]->dimm; in i82860_process_error_info()
162 csrow = mci->csrows[index]; in i82860_init_csrows()
H A Di3000_edac.c237 multi_chan = mci->csrows[0]->nr_channels - 1; in i3000_process_error_info()
392 struct csrow_info *csrow = mci->csrows[i]; in i3000_probe1()
H A Di82875p_edac.c229 multi_chan = mci->csrows[0]->nr_channels - 1; in i82875p_process_error_info()
362 csrow = mci->csrows[index]; in i82875p_init_csrows()
H A Dcpc925_edac.c337 csrow = mci->csrows[index]; in cpc925_init_csrows()
452 if (mci->csrows[rank]->first_page == 0) { in cpc925_mc_get_pfn()
460 pa = mci->csrows[rank]->first_page << PAGE_SHIFT; in cpc925_mc_get_pfn()
H A Dfsl_ddr_edac.c318 csrow = mci->csrows[row_index]; in fsl_mc_check()
444 csrow = mci->csrows[index]; in fsl_ddr_init_csrows()
H A Dr82600_edac.c231 csrow = mci->csrows[index]; in r82600_init_csrows()
H A Di82443bxgx_edac.c197 csrow = mci->csrows[index]; in i82443bxgx_init_csrows()
H A Dx38_edac.c373 struct csrow_info *csrow = mci->csrows[i]; in x38_probe1()
H A De7xxx_edac.c379 csrow = mci->csrows[index]; in e7xxx_init_csrows()
H A Ddmc520_edac.c460 csi = mci->csrows[row]; in dmc520_init_csrow()
H A Damd64_edac.c3094 dimm = mci->csrows[cs]->channels[umc]->dimm; in umc_init_csrows()
3143 csrow = mci->csrows[i]; in dct_init_csrows()
3591 dimm = mci->csrows[umc]->channels[cs]->dimm; in gpu_init_csrows()
H A De752x_edac.c1096 csrow = mci->csrows[remap_csrow_index(mci, index)]; in e752x_init_csrows()
H A Dversal_edac.c601 csi = mci->csrows[row]; in init_csrows()
H A Dsynopsys_edac.c857 csi = mci->csrows[row]; in init_csrows()
/linux/Documentation/admin-guide/RAS/
H A Dmain.rst333 There can be multiple csrows and multiple channels.
344 Memory controllers allow for several csrows, with 8 csrows being a
345 typical value. Yet, the actual number of csrows depends on the layout of
382 channel 1. Notice that there are two csrows possible on a physical DIMM.
383 These csrows are allocated their csrow assignment based on the slot into
385 Channel, the csrows cross both DIMMs.
1012 The minimum known unity is DIMMs. There are no information about csrows.
1013 As EDAC API maps the minimum unity is csrows, the driver sequentially
1014 maps channel/DIMM into different csrows.
1133 What happens here is that errors on different csrows, but at the same
/linux/include/linux/
H A Dedac.h541 struct csrow_info **csrows; member
/linux/Documentation/driver-api/
H A Dedac.rst219 They have chip selects (csrows) and channels. However, the layouts are different