| /linux/drivers/clk/ |
| H A D | clk-loongson2.c | 40 u8 div_width; member
53 u8 div_width; member
67 .div_width = _dwidth, \
81 .div_width = _dwidth, \
93 .div_width = _dwidth, \
219 div = loongson2_rate_part(val, clk->div_shift, clk->div_width); in loongson2_pll_recalc_rate()
235 mult = loongson2_rate_part(val, clk->div_shift, clk->div_width) + 1; in loongson2_freqscale_recalc_rate()
269 clk->div_width = cld->div_width; in loongson2_clk_register()
325 p->div_shift, p->div_width, in loongson2_clk_probe()
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| H A D | clk-sp7021.c | 53 int div_width; member
406 u32 max = 1 << clk->div_width; in sp_pll_calc_div()
423 } else if (clk->div_width == DIV_A) { in sp_pll_round_rate()
425 } else if (clk->div_width == DIV_TV) { in sp_pll_round_rate()
445 } else if (clk->div_width == DIV_A) { in sp_pll_recalc_rate()
447 } else if (clk->div_width == DIV_TV) { in sp_pll_recalc_rate()
473 u32 fbdiv = ((reg >> clk->div_shift) & ((1 << clk->div_width) - 1)) + 1; in sp_pll_recalc_rate()
492 } else if (clk->div_width == DIV_A) { in sp_pll_set_rate()
494 } else if (clk->div_width == DIV_TV) { in sp_pll_set_rate()
496 } else if (clk->div_width) { in sp_pll_set_rate()
[all …]
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| H A D | clk-bm1880.c | 121 s8 div_width; member
153 .div_width = _div_width, \
813 div_hws->div.width = clks->div_width; in bm1880_clk_register_composite()
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| H A D | clk-k210.c | 36 u8 div_width; member
56 .div_width = (_width), \
760 div_val = (reg >> cfg->div_shift) & GENMASK(cfg->div_width - 1, 0); in k210_clk_get_rate()
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| /linux/drivers/clk/rockchip/ |
| H A D | clk.h | 594 u8 div_width; member
617 .div_width = dw, \
639 .div_width = dw, \
657 .div_width = dw, \
675 .div_width = dw, \
715 .div_width = dw, \
734 .div_width = dw, \
750 .div_width = 16, \
865 .div_width = w, \
880 .div_width = w, \
[all …]
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| H A D | clk-ddr.c | 22 int div_width; member
94 int div_shift, int div_width, in rockchip_clk_register_ddrclk() argument
130 ddrclk->div_width = div_width; in rockchip_clk_register_ddrclk()
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| H A D | clk.c | 43 int div_offset, u8 div_shift, u8 div_width, u8 div_flags, in rockchip_clk_register_branch() argument
85 if (div_width > 0) { in rockchip_clk_register_branch()
98 div->width = div_width; in rockchip_clk_register_branch()
493 list->div_shift, list->div_width, in rockchip_clk_register_branches()
500 list->div_shift, list->div_width, in rockchip_clk_register_branches()
518 list->div_width, list->div_flags, in rockchip_clk_register_branches()
537 list->div_shift, list->div_width, in rockchip_clk_register_branches()
561 list->div_shift, list->div_width, in rockchip_clk_register_branches()
571 list->div_width, list->div_flags, in rockchip_clk_register_branches()
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| H A D | clk-half-divider.c | 163 u8 div_shift, u8 div_width, in rockchip_clk_register_halfdiv() argument
202 if (div_width > 0) { in rockchip_clk_register_halfdiv()
210 div->width = div_width; in rockchip_clk_register_halfdiv()
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| /linux/drivers/clk/x86/ |
| H A D | clk-cgu.h | 183 u8 div_width; member
233 .div_width = _width, \
273 .div_width = _width, \
293 .div_width = _width, \
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| H A D | clk-cgu.c | 31 list->div_width, list->div_val); in lgm_clk_register_fixed()
200 u8 width = list->div_width; in lgm_clk_register_divider()
252 list->div_width, list->div_val); in lgm_clk_register_fixed_factor()
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| /linux/drivers/clk/mediatek/ |
| H A D | clk-mtk.h | 191 unsigned char div_width; member
202 .div_width = _width, \
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| H A D | clk-mt8167-apmixedsys.c | 83 .div_width = _width, \
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| H A D | clk-mt8516.c | 475 .div_width = _width, \
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| H A D | clk-mt8167.c | 664 .div_width = _width, \
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| H A D | clk-mt8365.c | 548 .div_width = _width, \
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| H A D | clk-mtk.c | 419 mcd->div_width, mcd->clk_divider_flags, lock); in mtk_clk_register_dividers()
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| /linux/drivers/clk/socfpga/ |
| H A D | clk-gate-s10.c | 152 socfpga_clk->width = clks->div_width; in s10_register_gate()
210 socfpga_clk->width = clks->div_width; in agilex_register_gate()
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| H A D | stratix10-clk.h | 70 u8 div_width; member
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