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Searched refs:hwc (Results 1 – 25 of 107) sorted by relevance

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/linux/drivers/net/ethernet/microsoft/mana/
H A Dhw_channel.c14 down(&hwc->sema); in mana_hwc_get_msg_index()
403 hwc_cq->hwc = hwc; in mana_hwc_create_cq()
517 hwc_wq->hwc = hwc; in mana_hwc_create_wq()
680 mana_hwc_tx_event_handler, hwc, &hwc->cq); in mana_hwc_init_queues()
687 hwc->cq, &hwc->rxq); in mana_hwc_init_queues()
694 hwc->cq, &hwc->txq); in mana_hwc_init_queues()
717 hwc = kzalloc(sizeof(*hwc), GFP_KERNEL); in mana_hwc_create_channel()
718 if (!hwc) in mana_hwc_create_channel()
770 if (!hwc) in mana_hwc_destroy_channel()
785 mana_hwc_destroy_wq(hwc, hwc->txq); in mana_hwc_destroy_channel()
[all …]
/linux/drivers/net/ethernet/mellanox/mlx5/core/sf/
H A Dhw_table.c49 struct mlx5_sf_hwc_table *hwc; in mlx5_sf_sw_to_hw_id() local
66 if (table->hwc[i].max_fn && in mlx5_sf_table_fn_to_hwc()
68 fn_id < (table->hwc[i].start_fn_id + table->hwc[i].max_fn)) in mlx5_sf_table_fn_to_hwc()
69 return &table->hwc[i]; in mlx5_sf_table_fn_to_hwc()
82 if (!hwc->sfs) in mlx5_sf_hw_table_id_alloc()
91 if (hwc->sfs[i].allocated && hwc->sfs[i].usr_sfnum == usr_sfnum) in mlx5_sf_hw_table_id_alloc()
236 hwc->sfs = sfs; in mlx5_sf_hw_table_hwc_init()
237 hwc->max_fn = max_fn; in mlx5_sf_hw_table_hwc_init()
244 kfree(hwc->sfs); in mlx5_sf_hw_table_hwc_cleanup()
357 if (!hwc) in mlx5_sf_hw_vhca_event()
[all …]
/linux/drivers/iio/buffer/
H A Dindustrialio-hw-consumer.c86 struct iio_hw_consumer *hwc; in iio_hw_consumer_alloc() local
90 hwc = kzalloc(sizeof(*hwc), GFP_KERNEL); in iio_hw_consumer_alloc()
91 if (!hwc) in iio_hw_consumer_alloc()
94 INIT_LIST_HEAD(&hwc->buffers); in iio_hw_consumer_alloc()
97 if (IS_ERR(hwc->channels)) { in iio_hw_consumer_alloc()
98 ret = PTR_ERR(hwc->channels); in iio_hw_consumer_alloc()
102 chan = &hwc->channels[0]; in iio_hw_consumer_alloc()
113 return hwc; in iio_hw_consumer_alloc()
118 iio_channel_release_all(hwc->channels); in iio_hw_consumer_alloc()
120 kfree(hwc); in iio_hw_consumer_alloc()
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/linux/arch/alpha/kernel/
H A Dperf_event.c414 int idx = hwc->idx; in maybe_change_configuration()
528 alpha_perf_event_update(event, hwc, hwc->idx, 0); in alpha_pmu_read()
543 alpha_perf_event_update(event, hwc, hwc->idx, 0); in alpha_pmu_stop()
562 alpha_perf_event_set_period(event, hwc, hwc->idx); in alpha_pmu_start()
565 hwc->state = 0; in alpha_pmu_start()
642 hwc->event_base = ev; in __hw_perf_event_init()
663 hwc->config_base = 0; in __hw_perf_event_init()
664 hwc->idx = PMC_NO_INDEX; in __hw_perf_event_init()
680 hwc->last_period = hwc->sample_period; in __hw_perf_event_init()
681 local64_set(&hwc->period_left, hwc->sample_period); in __hw_perf_event_init()
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/linux/drivers/perf/
H A Driscv_pmu.c151 if (hwc->idx == -1) in riscv_pmu_ctr_get_width_mask()
213 hwc->last_period = period; in riscv_pmu_event_set_period()
220 hwc->last_period = period; in riscv_pmu_event_set_period()
250 hwc->state = 0; in riscv_pmu_start()
268 hwc->idx = idx; in riscv_pmu_add()
296 hwc->idx = -1; in riscv_pmu_del()
316 hwc->flags = 0; in riscv_pmu_event_init()
330 hwc->config = event_config; in riscv_pmu_event_init()
331 hwc->idx = -1; in riscv_pmu_event_init()
346 hwc->last_period = hwc->sample_period; in riscv_pmu_event_init()
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H A Dthunderx2_pmu.c379 local64_set(&hwc->prev_count, 0); in uncore_start_event_l3c()
380 reg_writel(0, hwc->event_base); in uncore_start_event_l3c()
409 local64_set(&hwc->prev_count, 0); in uncore_start_event_dmc()
410 reg_writel(0, hwc->event_base); in uncore_start_event_dmc()
596 hwc->config = event->attr.config; in tx2_uncore_event_init()
610 hwc->state = 0; in tx2_uncore_event_start()
640 hwc->state |= PERF_HES_STOPPED; in tx2_uncore_event_stop()
643 hwc->state |= PERF_HES_UPTODATE; in tx2_uncore_event_stop()
656 if (hwc->idx < 0) in tx2_uncore_event_add()
683 tx2_pmu->events[hwc->idx] = NULL; in tx2_uncore_event_del()
[all …]
H A Darm_xscale_pmu.c175 struct hw_perf_event *hwc; in xscale1pmu_handle_irq() local
183 hwc = &event->hw; in xscale1pmu_handle_irq()
208 int idx = hwc->idx; in xscale1pmu_enable_event()
240 int idx = hwc->idx; in xscale1pmu_disable_event()
314 int counter = hwc->idx; in xscale1pmu_read_counter()
335 int counter = hwc->idx; in xscale1pmu_write_counter()
516 hwc = &event->hw; in xscale2pmu_handle_irq()
541 int idx = hwc->idx; in xscale2pmu_enable_event()
583 int idx = hwc->idx; in xscale2pmu_disable_event()
664 int counter = hwc->idx; in xscale2pmu_read_counter()
[all …]
H A Darm_pmu.c213 hwc->last_period = period; in armpmu_event_set_period()
300 hwc->state = 0; in armpmu_start()
318 int idx = hwc->idx; in armpmu_del()
325 hwc->idx = -1; in armpmu_del()
450 hwc->flags = 0; in __hw_perf_event_init()
465 hwc->idx = -1; in __hw_perf_event_init()
466 hwc->config_base = 0; in __hw_perf_event_init()
467 hwc->config = 0; in __hw_perf_event_init()
468 hwc->event_base = 0; in __hw_perf_event_init()
492 hwc->last_period = hwc->sample_period; in __hw_perf_event_init()
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H A Dstarfive_starlink_pmu.c167 local64_set(&hwc->prev_count, val); in starlink_pmu_set_event_period()
168 if (hwc->config == STARLINK_CYCLES) in starlink_pmu_set_event_period()
224 if (hwc->config == STARLINK_CYCLES) in starlink_pmu_counter_stop()
236 int idx = hwc->idx; in starlink_pmu_update()
269 hwc->state = 0; in starlink_pmu_start()
282 if (hwc->state & PERF_HES_STOPPED) in starlink_pmu_stop()
318 hwc->idx = idx; in starlink_pmu_add()
338 hw_events->events[hwc->idx] = NULL; in starlink_pmu_del()
377 if (hwc->sample_period) in starlink_pmu_event_init()
390 hwc->idx = -1; in starlink_pmu_event_init()
[all …]
H A Dqcom_l2_pmu.c301 u32 idx = hwc->idx; in l2_cache_event_update()
322 u32 idx = hwc->idx; in l2_cache_cluster_set_period()
378 int idx = hwc->idx; in l2_cache_clear_event_idx()
407 hwc = &event->hw; in l2_cache_handle_irq()
450 if (hwc->sample_period) { in l2_cache_event_init()
529 hwc->idx = -1; in l2_cache_event_init()
545 int idx = hwc->idx; in l2_cache_event_start()
549 hwc->state = 0; in l2_cache_event_start()
575 int idx = hwc->idx; in l2_cache_event_stop()
601 hwc->idx = idx; in l2_cache_event_add()
[all …]
H A Dmarvell_cn10k_ddr_pmu.c350 hwc->idx = -1; in cn10k_ddr_perf_event_init()
426 int counter = hwc->idx; in cn10k_ddr_perf_event_start()
432 hwc->state = 0; in cn10k_ddr_perf_event_start()
449 hwc->idx = counter; in cn10k_ddr_perf_event_add()
485 int counter = hwc->idx; in cn10k_ddr_perf_event_stop()
499 int counter = hwc->idx; in cn10k_ddr_perf_event_del()
505 hwc->idx = -1; in cn10k_ddr_perf_event_del()
530 struct hw_perf_event *hwc; in cn10k_ddr_perf_event_update_all() local
553 struct hw_perf_event *hwc; in cn10k_ddr_pmu_overflow_handler() local
560 hwc = &event->hw; in cn10k_ddr_pmu_overflow_handler()
[all …]
/linux/arch/loongarch/kernel/
H A Dperf_event.c363 hwc->state = 0; in loongarch_pmu_start()
366 loongarch_pmu_event_set_period(event, hwc, hwc->idx); in loongarch_pmu_start()
369 loongarch_pmu_enable_event(hwc, hwc->idx); in loongarch_pmu_start()
380 loongarch_pmu_event_update(event, hwc, hwc->idx); in loongarch_pmu_stop()
424 int idx = hwc->idx; in loongarch_pmu_del()
440 if (hwc->idx < 0) in loongarch_pmu_read()
443 loongarch_pmu_event_update(event, hwc, hwc->idx); in loongarch_pmu_read()
792 hwc->idx = -1; in __hw_perf_event_init()
793 hwc->config = 0; in __hw_perf_event_init()
797 hwc->last_period = hwc->sample_period; in __hw_perf_event_init()
[all …]
/linux/arch/x86/events/amd/
H A Diommu.c241 u8 bank = hwc->iommu_bank; in perf_iommu_enable_event()
242 u8 cntr = hwc->iommu_cntr; in perf_iommu_enable_event()
245 reg = GET_CSOURCE(hwc); in perf_iommu_enable_event()
248 reg = GET_DEVID_MASK(hwc); in perf_iommu_enable_event()
254 reg = GET_PASID_MASK(hwc); in perf_iommu_enable_event()
260 reg = GET_DOMID_MASK(hwc); in perf_iommu_enable_event()
273 amd_iommu_pc_set_reg(iommu, hwc->iommu_bank, hwc->iommu_cntr, in perf_iommu_disable_event()
285 hwc->state = 0; in perf_iommu_start()
302 amd_iommu_pc_set_reg(iommu, hwc->iommu_bank, hwc->iommu_cntr, in perf_iommu_start()
315 if (amd_iommu_pc_get_reg(iommu, hwc->iommu_bank, hwc->iommu_cntr, in perf_iommu_read()
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H A Duncore.c124 wrmsrl(hwc->event_base, (u64)local64_read(&hwc->prev_count)); in amd_uncore_start()
126 hwc->state = 0; in amd_uncore_start()
135 wrmsrl(hwc->config_base, hwc->config); in amd_uncore_stop()
152 if (hwc->idx != -1 && ctx->events[hwc->idx] == event) in amd_uncore_add()
157 hwc->idx = i; in amd_uncore_add()
163 hwc->idx = -1; in amd_uncore_add()
177 hwc->config_base = pmu->msr_base + (2 * hwc->idx); in amd_uncore_add()
178 hwc->event_base = pmu->msr_base + 1 + (2 * hwc->idx); in amd_uncore_add()
179 hwc->event_base_rdpmc = pmu->rdpmc_base + hwc->idx; in amd_uncore_add()
207 hwc->idx = -1; in amd_uncore_del()
[all …]
H A Dibs.c113 hwc->last_period = period; in perf_event_set_period()
120 hwc->last_period = period; in perf_event_set_period()
297 if (hwc->sample_period) { in perf_ibs_init()
309 if (!hwc->sample_period) in perf_ibs_init()
318 if (!hwc->sample_period) in perf_ibs_init()
325 hwc->last_period = hwc->sample_period; in perf_ibs_init()
326 local64_set(&hwc->period_left, hwc->sample_period); in perf_ibs_init()
329 hwc->config = config; in perf_ibs_init()
436 hwc->state = 0; in perf_ibs_start()
1052 hwc = &event->hw; in perf_ibs_handle_irq()
[all …]
/linux/drivers/perf/hisilicon/
H A Dhisi_uncore_pmu.c172 struct hw_perf_event *hwc = &event->hw; in hisi_uncore_pmu_event_init() local
211 hwc->idx = -1; in hisi_uncore_pmu_event_init()
212 hwc->config_base = event->attr.config; in hisi_uncore_pmu_event_init()
231 struct hw_perf_event *hwc = &event->hw; in hisi_uncore_pmu_enable_event() local
249 struct hw_perf_event *hwc = &event->hw; in hisi_uncore_pmu_disable_event() local
261 struct hw_perf_event *hwc = &event->hw; in hisi_uncore_pmu_set_event_period() local
272 local64_set(&hwc->prev_count, val); in hisi_uncore_pmu_set_event_period()
308 hwc->state = 0; in hisi_uncore_pmu_start()
328 hwc->state |= PERF_HES_STOPPED; in hisi_uncore_pmu_stop()
330 if (hwc->state & PERF_HES_UPTODATE) in hisi_uncore_pmu_stop()
[all …]
H A Dhisi_uncore_ddrc_pmu.c59 #define GET_DDRC_EVENTID(hwc) (hwc->config_base & 0x7) argument
96 struct hw_perf_event *hwc) in hisi_ddrc_pmu_v2_read_counter() argument
212 val |= 1 << hwc->idx; in hisi_ddrc_pmu_v2_enable_counter()
222 val &= ~(1 << hwc->idx); in hisi_ddrc_pmu_v2_disable_counter()
227 struct hw_perf_event *hwc) in hisi_ddrc_pmu_v1_enable_counter_int() argument
233 val &= ~(1 << hwc->idx); in hisi_ddrc_pmu_v1_enable_counter_int()
244 val |= 1 << hwc->idx; in hisi_ddrc_pmu_v1_disable_counter_int()
249 struct hw_perf_event *hwc) in hisi_ddrc_pmu_v2_enable_counter_int() argument
254 val &= ~(1 << hwc->idx); in hisi_ddrc_pmu_v2_enable_counter_int()
259 struct hw_perf_event *hwc) in hisi_ddrc_pmu_v2_disable_counter_int() argument
[all …]
H A Dhisi_pcie_pmu.c393 hwc->event_base = HISI_PCIE_CNT; in hisi_pcie_pmu_event_init()
470 int idx = hwc->idx; in hisi_pcie_pmu_set_period()
493 u32 idx = hwc->idx; in hisi_pcie_pmu_enable_counter()
503 u32 idx = hwc->idx; in hisi_pcie_pmu_disable_counter()
513 u32 idx = hwc->idx; in hisi_pcie_pmu_enable_int()
520 u32 idx = hwc->idx; in hisi_pcie_pmu_disable_int()
535 int idx = hwc->idx; in hisi_pcie_pmu_start()
542 hwc->state = 0; in hisi_pcie_pmu_start()
567 hwc->state |= PERF_HES_STOPPED; in hisi_pcie_pmu_stop()
572 hwc->state |= PERF_HES_UPTODATE; in hisi_pcie_pmu_stop()
[all …]
/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_pmu.c241 hwc->state = 0; in amdgpu_perf_start()
243 switch (hwc->config_base) { in amdgpu_perf_start()
253 hwc->idx = target_cntr; in amdgpu_perf_start()
257 hwc->idx, 0); in amdgpu_perf_start()
285 hwc->config, hwc->idx, &count); in amdgpu_perf_read()
311 switch (hwc->config_base) { in amdgpu_perf_stop()
314 pe->adev->df.funcs->pmc_stop(pe->adev, hwc->config, hwc->idx, in amdgpu_perf_stop()
349 hwc->config_base = (hwc->config >> in amdgpu_perf_add()
357 switch (hwc->config_base) { in amdgpu_perf_add()
366 hwc->idx = target_cntr; in amdgpu_perf_add()
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/linux/arch/xtensa/kernel/
H A Dperf_event.c172 s64 period = hwc->sample_period; in xtensa_perf_event_set_period()
178 hwc->last_period = period; in xtensa_perf_event_set_period()
183 hwc->last_period = period; in xtensa_perf_event_set_period()
190 local64_set(&hwc->prev_count, -left); in xtensa_perf_event_set_period()
252 int idx = hwc->idx; in xtensa_pmu_start()
262 hwc->state = 0; in xtensa_pmu_start()
270 int idx = hwc->idx; in xtensa_pmu_stop()
276 hwc->state |= PERF_HES_STOPPED; in xtensa_pmu_stop()
294 int idx = hwc->idx; in xtensa_pmu_add()
303 hwc->idx = idx; in xtensa_pmu_add()
[all …]
/linux/arch/arc/kernel/
H A Dperf_event.c336 hwc->last_period = hwc->sample_period; in arc_pmu_event_init()
337 local64_set(&hwc->period_left, hwc->sample_period); in arc_pmu_event_init()
340 hwc->config = 0; in arc_pmu_event_init()
410 int idx = hwc->idx; in arc_pmu_event_set_period()
418 hwc->last_period = period; in arc_pmu_event_set_period()
424 hwc->last_period = period; in arc_pmu_event_set_period()
454 int idx = hwc->idx; in arc_pmu_start()
462 hwc->state = 0; in arc_pmu_start()
479 int idx = hwc->idx; in arc_pmu_stop()
533 hwc->idx = idx; in arc_pmu_add()
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/linux/arch/s390/kernel/
H A Dperf_cpum_sf.c35 #define OVERFLOW_REG(hwc) ((hwc)->extra_reg.config) argument
36 #define SFB_ALLOC_REG(hwc) ((hwc)->extra_reg.alloc) argument
37 #define TEAR_REG(hwc) ((hwc)->last_tag) argument
38 #define SAMPL_RATE(hwc) ((hwc)->event_base) argument
39 #define SAMPL_FLAGS(hwc) ((hwc)->config_base) argument
40 #define SAMPL_DIAG_MODE(hwc) (SAMPL_FLAGS(hwc) & PERF_CPUM_SF_DIAG_MODE) argument
605 hwc->last_period = hwc->sample_period; in hw_init_period()
606 local64_set(&hwc->period_left, hwc->sample_period); in hw_init_period()
744 hw_init_period(hwc, SAMPL_RATE(hwc)); in __hw_perf_event_init_rate()
1264 OVERFLOW_REG(hwc) = DIV_ROUND_UP(OVERFLOW_REG(hwc) + in hw_perf_event_update()
[all …]
/linux/arch/x86/events/intel/
H A Duncore_nhmex.c248 struct hw_perf_event *hwc = &event->hw; in nhmex_uncore_msr_enable_event() local
250 if (hwc->idx == UNCORE_PMC_IDX_FIXED) in nhmex_uncore_msr_enable_event()
253 wrmsrl(hwc->config_base, hwc->config | NHMEX_PMON_CTL_EN_BIT22); in nhmex_uncore_msr_enable_event()
255 wrmsrl(hwc->config_base, hwc->config | NHMEX_PMON_CTL_EN_BIT0); in nhmex_uncore_msr_enable_event()
353 struct hw_perf_event *hwc = &event->hw; in nhmex_bbox_hw_config() local
380 struct hw_perf_event *hwc = &event->hw; in nhmex_bbox_msr_enable_event() local
475 wrmsrl(hwc->config_base, hwc->config | NHMEX_PMON_CTL_EN_BIT22); in nhmex_sbox_msr_enable_event()
863 wrmsrl(hwc->config_base, hwc->config | NHMEX_PMON_CTL_EN_BIT0); in nhmex_mbox_msr_enable_event()
1029 er->config = (hwc->config >> 32); in nhmex_rbox_get_constraint()
1136 hwc->config >> 32); in nhmex_rbox_msr_enable_event()
[all …]
H A Duncore_discovery.c460 struct hw_perf_event *hwc = &event->hw; in intel_generic_uncore_msr_enable_event() local
462 wrmsrl(hwc->config_base, hwc->config); in intel_generic_uncore_msr_enable_event()
470 wrmsrl(hwc->config_base, 0); in intel_generic_uncore_msr_disable_event()
492 hwc->config_base = uncore_pci_event_ctl(box, hwc->idx); in intel_generic_uncore_assign_hw_event()
493 hwc->event_base = uncore_pci_perf_ctr(box, hwc->idx); in intel_generic_uncore_assign_hw_event()
503 hwc->config_base = box_ctl + uncore_pci_event_ctl(box, hwc->idx); in intel_generic_uncore_assign_hw_event()
504 hwc->event_base = box_ctl + uncore_pci_perf_ctr(box, hwc->idx); in intel_generic_uncore_assign_hw_event()
508 hwc->config_base = box_ctl + box->pmu->type->event_ctl + hwc->idx; in intel_generic_uncore_assign_hw_event()
509 hwc->event_base = box_ctl + box->pmu->type->perf_ctr + hwc->idx; in intel_generic_uncore_assign_hw_event()
550 pci_write_config_dword(pdev, hwc->config_base, hwc->config); in intel_generic_uncore_pci_enable_event()
[all …]
/linux/arch/sh/kernel/
H A Dperf_event.c103 struct hw_perf_event *hwc = &event->hw; in __hw_perf_event_init() local
153 hwc->config |= config; in __hw_perf_event_init()
202 struct hw_perf_event *hwc = &event->hw; in sh_pmu_stop() local
203 int idx = hwc->idx; in sh_pmu_stop()
206 sh_pmu->disable(hwc, idx); in sh_pmu_stop()
220 struct hw_perf_event *hwc = &event->hw; in sh_pmu_start() local
221 int idx = hwc->idx; in sh_pmu_start()
231 sh_pmu->enable(hwc, idx); in sh_pmu_start()
248 int idx = hwc->idx; in sh_pmu_add()
259 hwc->idx = idx; in sh_pmu_add()
[all …]

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