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Searched refs:ih_regs (Results 1 – 7 of 7) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvega10_ih.c49 struct amdgpu_ih_regs *ih_regs; in vega10_ih_init_register_offset() local
52 ih_regs = &adev->irq.ih.ih_regs; in vega10_ih_init_register_offset()
65 ih_regs = &adev->irq.ih1.ih_regs; in vega10_ih_init_register_offset()
76 ih_regs = &adev->irq.ih2.ih_regs; in vega10_ih_init_register_offset()
100 struct amdgpu_ih_regs *ih_regs; in vega10_ih_toggle_ring_interrupts() local
103 ih_regs = &ih->ih_regs; in vega10_ih_toggle_ring_interrupts()
211 struct amdgpu_ih_regs *ih_regs; in vega10_ih_enable_ring() local
214 ih_regs = &ih->ih_regs; in vega10_ih_enable_ring()
353 ih_regs = &ih->ih_regs; in vega10_ih_get_wptr()
400 ih_regs = &ih->ih_regs; in vega10_ih_irq_rearm()
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H A Dnavi10_ih.c51 struct amdgpu_ih_regs *ih_regs; in navi10_ih_init_register_offset() local
54 ih_regs = &adev->irq.ih.ih_regs; in navi10_ih_init_register_offset()
67 ih_regs = &adev->irq.ih1.ih_regs; in navi10_ih_init_register_offset()
78 ih_regs = &adev->irq.ih2.ih_regs; in navi10_ih_init_register_offset()
156 struct amdgpu_ih_regs *ih_regs; in navi10_ih_toggle_ring_interrupts() local
159 ih_regs = &ih->ih_regs; in navi10_ih_toggle_ring_interrupts()
266 struct amdgpu_ih_regs *ih_regs; in navi10_ih_enable_ring() local
269 ih_regs = &ih->ih_regs; in navi10_ih_enable_ring()
424 ih_regs = &ih->ih_regs; in navi10_ih_get_wptr()
469 ih_regs = &ih->ih_regs; in navi10_ih_irq_rearm()
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H A Dvega20_ih.c57 struct amdgpu_ih_regs *ih_regs; in vega20_ih_init_register_offset() local
60 ih_regs = &adev->irq.ih.ih_regs; in vega20_ih_init_register_offset()
73 ih_regs = &adev->irq.ih1.ih_regs; in vega20_ih_init_register_offset()
84 ih_regs = &adev->irq.ih2.ih_regs; in vega20_ih_init_register_offset()
108 struct amdgpu_ih_regs *ih_regs; in vega20_ih_toggle_ring_interrupts() local
111 ih_regs = &ih->ih_regs; in vega20_ih_toggle_ring_interrupts()
220 struct amdgpu_ih_regs *ih_regs; in vega20_ih_enable_ring() local
223 ih_regs = &ih->ih_regs; in vega20_ih_enable_ring()
405 ih_regs = &ih->ih_regs; in vega20_ih_get_wptr()
452 ih_regs = &ih->ih_regs; in vega20_ih_irq_rearm()
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H A Dih_v6_0.c48 struct amdgpu_ih_regs *ih_regs; in ih_v6_0_init_register_offset() local
53 ih_regs = &adev->irq.ih.ih_regs; in ih_v6_0_init_register_offset()
66 ih_regs = &adev->irq.ih1.ih_regs; in ih_v6_0_init_register_offset()
131 struct amdgpu_ih_regs *ih_regs; in ih_v6_0_toggle_ring_interrupts() local
134 ih_regs = &ih->ih_regs; in ih_v6_0_toggle_ring_interrupts()
268 struct amdgpu_ih_regs *ih_regs; in ih_v6_0_enable_ring() local
271 ih_regs = &ih->ih_regs; in ih_v6_0_enable_ring()
302 WREG32(ih_regs->ih_rb_wptr, 0); in ih_v6_0_enable_ring()
441 ih_regs = &ih->ih_regs; in ih_v6_0_get_wptr()
488 ih_regs = &ih->ih_regs; in ih_v6_0_irq_rearm()
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H A Dih_v6_1.c48 struct amdgpu_ih_regs *ih_regs; in ih_v6_1_init_register_offset() local
53 ih_regs = &adev->irq.ih.ih_regs; in ih_v6_1_init_register_offset()
66 ih_regs = &adev->irq.ih1.ih_regs; in ih_v6_1_init_register_offset()
131 struct amdgpu_ih_regs *ih_regs; in ih_v6_1_toggle_ring_interrupts() local
134 ih_regs = &ih->ih_regs; in ih_v6_1_toggle_ring_interrupts()
240 struct amdgpu_ih_regs *ih_regs; in ih_v6_1_enable_ring() local
243 ih_regs = &ih->ih_regs; in ih_v6_1_enable_ring()
274 WREG32(ih_regs->ih_rb_wptr, 0); in ih_v6_1_enable_ring()
413 ih_regs = &ih->ih_regs; in ih_v6_1_get_wptr()
461 ih_regs = &ih->ih_regs; in ih_v6_1_irq_rearm()
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H A Dih_v7_0.c48 struct amdgpu_ih_regs *ih_regs; in ih_v7_0_init_register_offset() local
53 ih_regs = &adev->irq.ih.ih_regs; in ih_v7_0_init_register_offset()
66 ih_regs = &adev->irq.ih1.ih_regs; in ih_v7_0_init_register_offset()
131 struct amdgpu_ih_regs *ih_regs; in ih_v7_0_toggle_ring_interrupts() local
134 ih_regs = &ih->ih_regs; in ih_v7_0_toggle_ring_interrupts()
240 struct amdgpu_ih_regs *ih_regs; in ih_v7_0_enable_ring() local
243 ih_regs = &ih->ih_regs; in ih_v7_0_enable_ring()
274 WREG32(ih_regs->ih_rb_wptr, 0); in ih_v7_0_enable_ring()
413 ih_regs = &ih->ih_regs; in ih_v7_0_get_wptr()
460 ih_regs = &ih->ih_regs; in ih_v7_0_irq_rearm()
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H A Damdgpu_ih.h70 struct amdgpu_ih_regs ih_regs; member