Searched refs:iobase_addr (Results 1 – 6 of 6) sorted by relevance
301 wrt_reg_dword(®->iobase_addr, iobase); in qla24xx_read_window()1135 wrt_reg_dword(®->iobase_addr, 0x0F70); in qla24xx_fw_dump()1136 rd_reg_dword(®->iobase_addr); in qla24xx_fw_dump()1374 wrt_reg_dword(®->iobase_addr, 0x7C00); in qla25xx_fw_dump()1375 rd_reg_dword(®->iobase_addr); in qla25xx_fw_dump()1399 rd_reg_dword(®->iobase_addr); in qla25xx_fw_dump()1686 rd_reg_dword(®->iobase_addr); in qla81xx_fw_dump()1710 rd_reg_dword(®->iobase_addr); in qla81xx_fw_dump()2010 rd_reg_dword(®->iobase_addr); in qla83xx_fw_dump()2021 rd_reg_dword(®->iobase_addr); in qla83xx_fw_dump()[all …]
10 #define IOBASE_ADDR offsetof(struct device_reg_24xx, iobase_addr)
10 #define IOBAR(reg) offsetof(typeof(*(reg)), iobase_addr)
1275 __le32 iobase_addr; /* I/O Bus Base Address register. */ member
4175 wrt_reg_dword(®->iobase_addr, 0x7C00); in qla2xxx_check_risc_status()4176 rd_reg_dword(®->iobase_addr); in qla2xxx_check_risc_status()
3465 wrt_reg_dword(®->iobase_addr, RISC_REGISTER_BASE_OFFSET); in qla25xx_read_risc_sema_reg()3474 wrt_reg_dword(®->iobase_addr, RISC_REGISTER_BASE_OFFSET); in qla25xx_write_risc_sema_reg()