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Searched refs:plane_res (Results 1 – 25 of 46) sorted by relevance

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/linux/drivers/gpu/drm/amd/display/dc/dce60/
H A Ddce60_hw_sequencer.c247 pipe_ctx->plane_res.xfm, in dce60_program_scaler()
265 pipe_ctx->plane_res.xfm->funcs->transform_set_scaler(pipe_ctx->plane_res.xfm, in dce60_program_scaler()
266 &pipe_ctx->plane_res.scl_data); in dce60_program_scaler()
299 (pipe_ctx->plane_res.xfm, &tbl_entry); in dce60_program_front_end_for_pipe()
310 pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust); in dce60_program_front_end_for_pipe()
329 pipe_ctx->plane_res.mi, in dce60_program_front_end_for_pipe()
373 pipe_ctx->plane_res.scl_data.viewport.x, in dce60_program_front_end_for_pipe()
374 pipe_ctx->plane_res.scl_data.viewport.y, in dce60_program_front_end_for_pipe()
377 pipe_ctx->plane_res.scl_data.recout.x, in dce60_program_front_end_for_pipe()
378 pipe_ctx->plane_res.scl_data.recout.y); in dce60_program_front_end_for_pipe()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dml/calcs/
H A Ddcn_calcs.c412 switch (pipe->plane_res.scl_data.lb_params.depth) { in pipe_ctx_to_e2e_pipe_params()
949 + pipe->plane_res.scl_data.viewport.x; in dcn_validate_bandwidth()
951 + pipe->bottom_pipe->plane_res.scl_data.viewport.x; in dcn_validate_bandwidth()
955 - pipe->bottom_pipe->plane_res.scl_data.viewport.x; in dcn_validate_bandwidth()
958 - pipe->plane_res.scl_data.viewport.x; in dcn_validate_bandwidth()
961 + pipe->plane_res.scl_data.viewport.y; in dcn_validate_bandwidth()
963 + pipe->bottom_pipe->plane_res.scl_data.viewport.y; in dcn_validate_bandwidth()
967 - pipe->bottom_pipe->plane_res.scl_data.viewport.y; in dcn_validate_bandwidth()
970 - pipe->plane_res.scl_data.viewport.y; in dcn_validate_bandwidth()
973 + pipe->bottom_pipe->plane_res.scl_data.recout.width; in dcn_validate_bandwidth()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/core/
H A Ddc_resource.c1167 pipe_ctx->plane_res.scl_data.ratios.horz_c = pipe_ctx->plane_res.scl_data.ratios.horz; in calculate_scaling_ratios()
1168 pipe_ctx->plane_res.scl_data.ratios.vert_c = pipe_ctx->plane_res.scl_data.ratios.vert; in calculate_scaling_ratios()
1552 pipe_ctx->plane_res.xfm, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality); in resource_build_scaling_params()
1556 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality); in resource_build_scaling_params()
1565 pipe_ctx->plane_res.xfm, in resource_build_scaling_params()
1571 pipe_ctx->plane_res.dpp, in resource_build_scaling_params()
1593 pipe_ctx->plane_res.scl_data.recout.y += pipe_ctx->plane_res.scl_data.recout.height; in resource_build_scaling_params()
1595 pipe_ctx->plane_res.scl_data.recout.x += pipe_ctx->plane_res.scl_data.recout.width; in resource_build_scaling_params()
2256 pipe->plane_res.dpp->inst, in resource_log_pipe()
2272 pipe->plane_res.dpp->inst, in resource_log_pipe()
[all …]
H A Ddc_stream.c351 (!pipe_ctx->plane_res.mi && !pipe_ctx->plane_res.hubp) || in program_cursor_position()
353 (!pipe_ctx->plane_res.xfm && !pipe_ctx->plane_res.dpp) || in program_cursor_position()
354 (!pipe_ctx->plane_res.ipp && !pipe_ctx->plane_res.dpp)) in program_cursor_position()
445 pipe_ctx->plane_res.hubp->mpcc_id); in dc_stream_program_cursor_position()
764 hubp = pipe_ctx->plane_res.hubp; in dc_stream_set_dynamic_metadata()
H A Ddc_surface.c76 if (pipe_ctx->plane_state == plane_state && pipe_ctx->plane_res.hubp) in dc_plane_get_pipe_mask()
77 pipe_mask |= 1 << pipe_ctx->plane_res.hubp->inst; in dc_plane_get_pipe_mask()
H A Ddc_hw_sequencer.c336 switch (pipe_ctx->plane_res.scl_data.format) { in get_surface_visual_confirm_color()
393 switch (top_pipe_ctx->plane_res.scl_data.format) { in get_hdr_visual_confirm_color()
703 …ce[*num_steps].params.power_on_mpc_mem_pwr_params.mpcc_id = current_mpc_pipe->plane_res.hubp->inst; in hwss_build_fast_sequence()
881 struct dpp *dpp = pipe_ctx->plane_res.dpp; in hwss_setup_dpp()
904 struct dpp *dpp = pipe_ctx->plane_res.dpp; in hwss_program_bias_and_scale()
1077 hubp = pipe_ctx->plane_res.hubp; in hwss_wait_for_outstanding_hw_updates()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dce110/
H A Ddce110_hwseq.c1484 pipe_ctx->plane_res.xfm, in program_scaler()
1502 pipe_ctx->plane_res.xfm->funcs->transform_set_scaler(pipe_ctx->plane_res.xfm, in program_scaler()
2023 pipe_ctx->plane_res.mi, in dce110_set_displaymarks()
2032 pipe_ctx->plane_res.mi, in dce110_set_displaymarks()
2607 pipe_ctx->plane_res.mi, in update_plane_addr()
2623 pipe_ctx->plane_res.mi); in dce110_update_pending_status()
2626 pipe_ctx->plane_res.mi->current_address = pipe_ctx->plane_res.mi->request_address; in dce110_update_pending_status()
2934 pipe_ctx->plane_res.mi, in dce110_program_front_end_for_pipe()
3008 pipe_ctx->plane_res.mi, in dce110_apply_ctx_for_surface()
3128 if (pipe_ctx->plane_res.ipp && in dce110_set_cursor_attribute()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn35/
H A Ddcn35_hwseq.c887 pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true); in dcn35_enable_plane()
890 pipe_ctx->plane_res.hubp->funcs->hubp_init(pipe_ctx->plane_res.hubp); in dcn35_enable_plane()
913 pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int(pipe_ctx->plane_res.hubp); in dcn35_enable_plane()
947 memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res)); in dcn35_plane_atomic_disable()
961 if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated) in dcn35_disable_plane()
1010 if (pipe_ctx->plane_res.hubp) in dcn35_calc_blocks_to_gate()
1013 if (pipe_ctx->plane_res.dpp && pipe_ctx->plane_res.hubp) in dcn35_calc_blocks_to_gate()
1114 cur_pipe->plane_res.hubp != new_pipe->plane_res.hubp && in dcn35_calc_blocks_to_ungate()
1115 new_pipe->plane_res.hubp) in dcn35_calc_blocks_to_ungate()
1119 cur_pipe->plane_res.dpp != new_pipe->plane_res.dpp && in dcn35_calc_blocks_to_ungate()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/
H A Ddc_spl_translate.c91 spl_in->basic_in.format = (enum spl_pixel_format)pipe_ctx->plane_res.scl_data.format; in translate_SPL_in_params_from_pipe_ctx()
130 spl_in->basic_out.alpha_en = pipe_ctx->plane_res.scl_data.lb_params.alpha_en; in translate_SPL_in_params_from_pipe_ctx()
187 spl_in->h_active = pipe_ctx->plane_res.scl_data.h_active; in translate_SPL_in_params_from_pipe_ctx()
188 spl_in->v_active = pipe_ctx->plane_res.scl_data.v_active; in translate_SPL_in_params_from_pipe_ctx()
208 populate_rect_from_splrect(&pipe_ctx->plane_res.scl_data.recout, &spl_out->dscl_prog_data->recout); in translate_SPL_out_params_to_pipe_ctx()
210 …populate_ratios_from_splratios(&pipe_ctx->plane_res.scl_data.ratios, &spl_out->dscl_prog_data->rat… in translate_SPL_out_params_to_pipe_ctx()
212 …populate_rect_from_splrect(&pipe_ctx->plane_res.scl_data.viewport, &spl_out->dscl_prog_data->viewp… in translate_SPL_out_params_to_pipe_ctx()
214 …populate_rect_from_splrect(&pipe_ctx->plane_res.scl_data.viewport_c, &spl_out->dscl_prog_data->vie… in translate_SPL_out_params_to_pipe_ctx()
216 populate_taps_from_spltaps(&pipe_ctx->plane_res.scl_data.taps, &spl_out->dscl_prog_data->taps); in translate_SPL_out_params_to_pipe_ctx()
218 populate_inits_from_splinits(&pipe_ctx->plane_res.scl_data.inits, &spl_out->dscl_prog_data->init); in translate_SPL_out_params_to_pipe_ctx()
H A Ddc_trace.h31 pipe_ctx->stream, &pipe_ctx->plane_res, \
H A Ddc_dmub_srv.c413 fams_pipe_data->pipe_index[pipe_idx++] = head_pipe->plane_res.hubp->inst; in dc_dmub_srv_populate_fams_pipe_info()
418 fams_pipe_data->pipe_index[pipe_idx++] = split_pipe->plane_res.hubp->inst; in dc_dmub_srv_populate_fams_pipe_info()
834 …>pipe_config.subvp_data.phantom_split_pipe_index = phantom_pipe->bottom_pipe->plane_res.hubp->inst; in populate_subvp_cmd_pipe_info()
836 …ipe_config.subvp_data.phantom_split_pipe_index = phantom_pipe->next_odm_pipe->plane_res.hubp->inst; in populate_subvp_cmd_pipe_info()
996 const struct scaler_data *scl_data = &pipe_ctx->plane_res.scl_data; in dc_can_pipe_disable_cursor()
1012 r2 = test_pipe->plane_res.scl_data.recout; in dc_can_pipe_disable_cursor()
1024 r2_half = split_pipe->plane_res.scl_data.recout; in dc_can_pipe_disable_cursor()
1063 struct hubp *hubp = pipe_ctx->plane_res.hubp; in dc_build_cursor_update_payload0()
1157 pCtx->plane_res.hubp, pCtx->plane_res.dpp); in dc_send_update_cursor_info_to_dmu()
1167 pipe_idx, pCtx->plane_res.hubp, pCtx->plane_res.dpp); in dc_send_update_cursor_info_to_dmu()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn20/
H A Ddcn20_hwseq.c388 if (pipe_ctx->plane_res.hubp && pipe_ctx->plane_res.hubp->funcs) { in dcn20_program_triple_buffer()
719 pipe_ctx->plane_res.dpp, in dcn20_plane_atomic_disable()
724 memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res)); in dcn20_plane_atomic_disable()
740 if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated) in dcn20_disable_plane()
1300 pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true); in dcn20_enable_plane()
1303 pipe_ctx->plane_res.hubp->funcs->hubp_init(pipe_ctx->plane_res.hubp); in dcn20_enable_plane()
1363 pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int(pipe_ctx->plane_res.hubp); in dcn20_enable_plane()
1575 if (old_pipe->plane_res.dpp != new_pipe->plane_res.dpp in dcn20_detect_pipe_changes()
1580 if (old_pipe->plane_res.bw.dppclk_khz != new_pipe->plane_res.bw.dppclk_khz) in dcn20_detect_pipe_changes()
1742 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data); in dcn20_update_dchubp_dpp()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn201/
H A Ddcn201_hwseq.c150 pipe_ctx->plane_res.hubp, in dcn201_update_plane_addr()
313 pipe_ctx->plane_res.hubp = hubp; in dcn201_init_hw()
314 pipe_ctx->plane_res.dpp = dpp; in dcn201_init_hw()
315 pipe_ctx->plane_res.mpcc_inst = dpp->inst; in dcn201_init_hw()
346 pipe_ctx->plane_res.hubp = NULL; in dcn201_init_hw()
380 struct hubp *hubp = pipe_ctx->plane_res.hubp; in dcn201_plane_atomic_disconnect()
381 int dpp_id = pipe_ctx->plane_res.dpp->inst; in dcn201_plane_atomic_disconnect()
424 struct hubp *hubp = pipe_ctx->plane_res.hubp; in dcn201_update_mpcc()
563 pipe_ctx->plane_res.hubp, attributes); in dcn201_set_cursor_attribute()
565 pipe_ctx->plane_res.dpp, attributes); in dcn201_set_cursor_attribute()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn10/
H A Ddcn10_hwseq.c1326 pipe_ctx->plane_res.dpp, in dcn10_plane_atomic_disable()
1327 pipe_ctx->plane_res.hubp); in dcn10_plane_atomic_disable()
1331 memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res)); in dcn10_plane_atomic_disable()
1342 if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated) in dcn10_disable_plane()
1801 pipe_ctx->plane_res.hubp, in dcn10_update_plane_addr()
2534 pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true); in dcn10_enable_plane()
2552 pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int(pipe_ctx->plane_res.hubp); in dcn10_enable_plane()
2577 pipe_ctx->plane_res.dpp->funcs->dpp_set_gamut_remap(pipe_ctx->plane_res.dpp, &adjust); in dcn10_program_gamut_remap()
2607 pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment(pipe_ctx->plane_res.dpp, matrix); in dcn10_set_csc_adjustment_rgb_mpo_fix()
2636 pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment(pipe_ctx->plane_res.dpp, matrix); in dcn10_program_output_csc()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/
H A Ddcn401_hwseq.c457 int mpcc_id = pipe_ctx->plane_res.hubp->inst; in dcn401_get_mcm_lut_xable_from_pipe_ctx()
487 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn401_populate_mcm_luts()
488 struct hubp *hubp = pipe_ctx->plane_res.hubp; in dcn401_populate_mcm_luts()
660 struct hubp *hubp = pipe_ctx->plane_res.hubp; in dcn401_trigger_3dlut_dma_load()
671 int mpcc_id = pipe_ctx->plane_res.hubp->inst; in dcn401_set_mcm_luts()
716 int mpcc_id = pipe_ctx->plane_res.hubp->inst; in dcn401_set_output_transfer_func()
1063 r2 = test_pipe->plane_res.scl_data.recout; in dcn401_can_pipe_disable_cursor()
1103 struct hubp *hubp = pipe_ctx->plane_res.hubp; in dcn401_set_cursor_position()
1104 struct dpp *dpp = pipe_ctx->plane_res.dpp; in dcn401_set_cursor_position()
1491 pipe_ctx->plane_res.hubp->funcs->program_extended_blank(pipe_ctx->plane_res.hubp, in dcn401_optimize_bandwidth()
[all …]
/linux/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_trace.h386 const struct plane_resource *plane_res,
388 TP_ARGS(pipe_idx, plane_state, stream, plane_res, update_flags),
439 __entry->recout_x = plane_res->scl_data.recout.x;
440 __entry->recout_y = plane_res->scl_data.recout.y;
441 __entry->recout_w = plane_res->scl_data.recout.width;
442 __entry->recout_h = plane_res->scl_data.recout.height;
443 __entry->viewport_x = plane_res->scl_data.viewport.x;
444 __entry->viewport_y = plane_res->scl_data.viewport.y;
445 __entry->viewport_w = plane_res->scl_data.viewport.width;
446 __entry->viewport_h = plane_res->scl_data.viewport.height;
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn20/
H A Ddcn20_resource.c1490 next_odm_pipe->plane_res.mi = pool->mis[next_odm_pipe->pipe_idx]; in dcn20_split_stream_for_odm()
1492 next_odm_pipe->plane_res.ipp = pool->ipps[next_odm_pipe->pipe_idx]; in dcn20_split_stream_for_odm()
1494 next_odm_pipe->plane_res.dpp = pool->dpps[next_odm_pipe->pipe_idx]; in dcn20_split_stream_for_odm()
1513 struct scaler_data *sd = &prev_odm_pipe->plane_res.scl_data; in dcn20_split_stream_for_odm()
1530 sd = &next_odm_pipe->plane_res.scl_data; in dcn20_split_stream_for_odm()
1575 secondary_pipe->plane_res.mi = pool->mis[secondary_pipe->pipe_idx]; in dcn20_split_stream_for_mpc()
1812 memset(&odm_pipe->plane_res, 0, sizeof(odm_pipe->plane_res)); in dcn20_merge_pipes_for_validate()
1837 memset(&hsplit_pipe->plane_res, 0, sizeof(hsplit_pipe->plane_res)); in dcn20_merge_pipes_for_validate()
2192 sec_dpp_pipe->plane_res.hubp = pool->hubps[sec_dpp_pipe->pipe_idx]; in dcn20_acquire_free_pipe_for_layer()
2193 sec_dpp_pipe->plane_res.ipp = pool->ipps[sec_dpp_pipe->pipe_idx]; in dcn20_acquire_free_pipe_for_layer()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn30/
H A Ddcn30_hwseq.c224 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn30_set_blend_lut()
246 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn30_set_mpc_shaper_3dlut()
247 int mpcc_id = pipe_ctx->plane_res.hubp->inst; in dcn30_set_mpc_shaper_3dlut()
301 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn30_set_input_transfer_func()
341 int mpcc_id = pipe_ctx->plane_res.hubp->inst; in dcn30_program_gamut_remap()
355 pipe_ctx->plane_res.dpp->funcs->dpp_set_gamut_remap(pipe_ctx->plane_res.dpp, in dcn30_program_gamut_remap()
377 int mpcc_id = pipe_ctx->plane_res.hubp->inst; in dcn30_set_output_transfer_func()
592 wb_info.mpcc_inst = pipe_ctx->plane_res.mpcc_inst; in dcn30_program_all_writeback_pipes_in_tree()
869 struct hubp *hubp = pipe_ctx->plane_res.hubp; in dcn30_program_dmdata_engine()
/linux/drivers/gpu/drm/amd/display/dc/dml2/
H A Ddml2_mall_phantom.c62 full_vp_width_blk_aligned = ((pipe->plane_res.scl_data.viewport.x + in dml2_helper_calculate_num_ways_for_subvp()
63 pipe->plane_res.scl_data.viewport.width + mblk_width - 1) / mblk_width * mblk_width) + in dml2_helper_calculate_num_ways_for_subvp()
64 (pipe->plane_res.scl_data.viewport.x / mblk_width * mblk_width); in dml2_helper_calculate_num_ways_for_subvp()
126 memset(&pipe->plane_res, 0, sizeof(pipe->plane_res)); in merge_pipes_for_subvp()
140 memset(&pipe->plane_res, 0, sizeof(pipe->plane_res)); in merge_pipes_for_subvp()
H A Ddml2_utils.c273 pipe_ctx->pipe_dlg_param.recout_height = pipe_ctx->plane_res.scl_data.recout.height; in populate_pipe_ctx_dlg_params_from_dml()
274 pipe_ctx->pipe_dlg_param.recout_width = pipe_ctx->plane_res.scl_data.recout.width; in populate_pipe_ctx_dlg_params_from_dml()
275 pipe_ctx->pipe_dlg_param.full_recout_height = pipe_ctx->plane_res.scl_data.recout.height; in populate_pipe_ctx_dlg_params_from_dml()
276 pipe_ctx->pipe_dlg_param.full_recout_width = pipe_ctx->plane_res.scl_data.recout.width; in populate_pipe_ctx_dlg_params_from_dml()
335 …context->res_ctx.pipe_ctx[dc_pipe_ctx_index].plane_res.bw.dppclk_khz = dml_get_dppclk_calculated(&… in dml2_calculate_rq_and_dlg_params()
336 …w_ctx.bw.dcn.clk.dppclk_khz < context->res_ctx.pipe_ctx[dc_pipe_ctx_index].plane_res.bw.dppclk_khz) in dml2_calculate_rq_and_dlg_params()
337 …context->bw_ctx.bw.dcn.clk.dppclk_khz = context->res_ctx.pipe_ctx[dc_pipe_ctx_index].plane_res.bw.… in dml2_calculate_rq_and_dlg_params()
/linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/
H A Ddml21_translation_helper.c710 temp_pipe->plane_res.scl_data.taps = pipe->plane_res.scl_data.taps; in get_scaler_data_for_plane()
718 return &temp_pipe->plane_res.scl_data; in get_scaler_data_for_plane()
1147 pipe_ctx->pipe_dlg_param.recout_height = pipe_ctx->plane_res.scl_data.recout.height; in dml21_populate_pipe_ctx_dlg_params()
1148 pipe_ctx->pipe_dlg_param.recout_width = pipe_ctx->plane_res.scl_data.recout.width; in dml21_populate_pipe_ctx_dlg_params()
1149 pipe_ctx->pipe_dlg_param.full_recout_height = pipe_ctx->plane_res.scl_data.recout.height; in dml21_populate_pipe_ctx_dlg_params()
1150 pipe_ctx->pipe_dlg_param.full_recout_width = pipe_ctx->plane_res.scl_data.recout.width; in dml21_populate_pipe_ctx_dlg_params()
1172 mcache_pipe_config->plane0.viewport_x_start = pipe_ctx->plane_res.scl_data.viewport.x; in dml21_get_pipe_mcache_config()
1173 mcache_pipe_config->plane0.viewport_width = pipe_ctx->plane_res.scl_data.viewport.width; in dml21_get_pipe_mcache_config()
1175 mcache_pipe_config->plane1.viewport_x_start = pipe_ctx->plane_res.scl_data.viewport_c.x; in dml21_get_pipe_mcache_config()
1176 mcache_pipe_config->plane1.viewport_width = pipe_ctx->plane_res.scl_data.viewport_c.width; in dml21_get_pipe_mcache_config()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/
H A Ddcn32_resource_helpers.c44 struct hubp *hubp = pipe_ctx->plane_res.hubp; in dcn32_helper_calculate_mall_bytes_for_cursor()
133 memset(&pipe->plane_res, 0, sizeof(pipe->plane_res)); in dcn32_merge_pipes_for_subvp()
147 memset(&pipe->plane_res, 0, sizeof(pipe->plane_res)); in dcn32_merge_pipes_for_subvp()
H A Ddcn32_resource.c2707 idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx]; in dcn32_acquire_idle_pipe_for_head_pipe_in_layer()
2708 idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx]; in dcn32_acquire_idle_pipe_for_head_pipe_in_layer()
2709 idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx]; in dcn32_acquire_idle_pipe_for_head_pipe_in_layer()
2767 free_pipe->plane_res.ipp = pool->ipps[free_pipe->pipe_idx]; in dcn32_acquire_free_pipe_as_secondary_dpp_pipe()
2768 free_pipe->plane_res.dpp = pool->dpps[free_pipe->pipe_idx]; in dcn32_acquire_free_pipe_as_secondary_dpp_pipe()
2769 free_pipe->plane_res.mpcc_inst = in dcn32_acquire_free_pipe_as_secondary_dpp_pipe()
2797 free_pipe->plane_res.mi = pool->mis[free_pipe_idx]; in dcn32_acquire_free_pipe_as_secondary_opp_head()
2798 free_pipe->plane_res.hubp = pool->hubps[free_pipe_idx]; in dcn32_acquire_free_pipe_as_secondary_opp_head()
2799 free_pipe->plane_res.ipp = pool->ipps[free_pipe_idx]; in dcn32_acquire_free_pipe_as_secondary_opp_head()
2800 free_pipe->plane_res.xfm = pool->transforms[free_pipe_idx]; in dcn32_acquire_free_pipe_as_secondary_opp_head()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/
H A Drv1_clk_mgr.c169 pipe_ctx->plane_res.dpp->funcs->dpp_dppclk_control( in ramp_up_dispclk_with_dpp()
170 pipe_ctx->plane_res.dpp, in ramp_up_dispclk_with_dpp()
/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddmub_psr.c341 copy_settings_data->mpcc_inst = pipe_ctx->plane_res.mpcc_inst; in dmub_psr_copy_settings()
343 if (pipe_ctx->plane_res.dpp) in dmub_psr_copy_settings()
344 copy_settings_data->dpp_inst = pipe_ctx->plane_res.dpp->inst; in dmub_psr_copy_settings()

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