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Searched refs:sdmax_rlcx_rb_base_hi (Results 1 – 21 of 21) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_amdkfd_arcturus.c179 m->sdmax_rlcx_rb_base_hi); in kgd_arcturus_hqd_sdma_load()
H A Damdgpu_amdkfd_gc_9_4_3.c115 m->sdmax_rlcx_rb_base_hi); in kgd_gfx_v9_4_3_hqd_sdma_load()
H A Damdgpu_amdkfd_gfx_v8.c304 m->sdmax_rlcx_rb_base_hi); in kgd_hqd_sdma_load()
H A Damdgpu_amdkfd_gfx_v10_3.c415 m->sdmax_rlcx_rb_base_hi); in hqd_sdma_load_v10_3()
H A Damdgpu_amdkfd_gfx_v11.c400 m->sdmax_rlcx_rb_base_hi); in hqd_sdma_load_v11()
H A Damdgpu_amdkfd_gfx_v10.c429 m->sdmax_rlcx_rb_base_hi); in kgd_hqd_sdma_load()
H A Damdgpu_amdkfd_gfx_v9.c440 m->sdmax_rlcx_rb_base_hi); in kgd_hqd_sdma_load()
H A Dsdma_v6_0.c846 m->sdmax_rlcx_rb_base_hi = upper_32_bits(prop->hqd_base_gpu_addr >> 8); in sdma_v6_0_mqd_init()
H A Dsdma_v7_0.c868 m->sdmax_rlcx_rb_base_hi = upper_32_bits(prop->hqd_base_gpu_addr >> 8); in sdma_v7_0_mqd_init()
H A Dsdma_v5_2.c829 m->sdmax_rlcx_rb_base_hi = upper_32_bits(prop->hqd_base_gpu_addr >> 8); in sdma_v5_2_mqd_init()
H A Dsdma_v5_0.c979 m->sdmax_rlcx_rb_base_hi = upper_32_bits(prop->hqd_base_gpu_addr >> 8); in sdma_v5_0_mqd_init()
/linux/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_mqd_manager_v12.c336 m->sdmax_rlcx_rb_base_hi = upper_32_bits(q->queue_address >> 8); in update_mqd_sdma()
H A Dkfd_mqd_manager_v10.c375 m->sdmax_rlcx_rb_base_hi = upper_32_bits(q->queue_address >> 8); in update_mqd_sdma()
H A Dkfd_mqd_manager_vi.c371 m->sdmax_rlcx_rb_base_hi = upper_32_bits(q->queue_address >> 8); in update_mqd_sdma()
H A Dkfd_mqd_manager_v11.c435 m->sdmax_rlcx_rb_base_hi = upper_32_bits(q->queue_address >> 8); in update_mqd_sdma()
H A Dkfd_mqd_manager_v9.c484 m->sdmax_rlcx_rb_base_hi = upper_32_bits(q->queue_address >> 8); in update_mqd_sdma()
/linux/drivers/gpu/drm/amd/include/
H A Dvi_structs.h30 uint32_t sdmax_rlcx_rb_base_hi; member
H A Dv9_structs.h30 uint32_t sdmax_rlcx_rb_base_hi; member
H A Dv11_structs.h545 uint32_t sdmax_rlcx_rb_base_hi; // offset: 2 (0x2) member
H A Dv12_structs.h545 uint32_t sdmax_rlcx_rb_base_hi; // offset: 2 (0x2) member
H A Dv10_structs.h545 uint32_t sdmax_rlcx_rb_base_hi; member