| /minix/external/bsd/llvm/dist/llvm/lib/Target/Mips/ |
| H A D | Mips16ISelDAGToDAG.cpp | 259 case ISD::ADDE: { in selectNode()
262 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) || in selectNode()
267 if (Opcode == ISD::ADDE) { in selectNode()
|
| H A D | MipsSEISelDAGToDAG.cpp | 235 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) || in selectAddESubE()
671 case ISD::ADDE: { in selectNode()
|
| H A D | MipsSEISelLowering.cpp | 142 setTargetDAGCombine(ISD::ADDE); in MipsSETargetLowering()
1071 case ISD::ADDE: in PerformDAGCombine()
|
| /minix/external/bsd/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 214 ADDE, SUBE, enumerator
|
| H A D | SelectionDAG.h | 1080 case ISD::ADDE:
|
| /minix/external/bsd/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1386 setOperationAction(ISD::ADDE, MVT::i8, Expand); in HexagonTargetLowering()
1387 setOperationAction(ISD::ADDE, MVT::i16, Expand); in HexagonTargetLowering()
1388 setOperationAction(ISD::ADDE, MVT::i32, Expand); in HexagonTargetLowering()
1389 setOperationAction(ISD::ADDE, MVT::i64, Expand); in HexagonTargetLowering()
|
| /minix/external/bsd/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.h | 78 ADDE, // Add using carry enumerator
|
| H A D | ARMISelLowering.cpp | 677 setOperationAction(ISD::ADDE, MVT::i32, Custom); in ARMTargetLowering()
1044 case ARMISD::ADDE: return "ARMISD::ADDE"; in getTargetNodeName()
6278 case ISD::ADDE: Opc = ARMISD::ADDE; ExtraOp = true; break; in LowerADDC_ADDE_SUBC_SUBE()
6457 case ISD::ADDE: in LowerOperation()
8045 if (AddeNode->getOpcode() != ISD::ADDE) in AddCombineTo64bitMLAL()
10415 case ARMISD::ADDE: in computeKnownBitsForTargetNode()
|
| H A D | ARMInstrInfo.td | 157 def ARMadde : SDNode<"ARMISD::ADDE", SDTBinaryArithWithFlagsInOut>;
|
| /minix/external/bsd/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 209 case ISD::ADDE: return "adde"; in getOperationName()
|
| H A D | LegalizeIntegerTypes.cpp | 1302 case ISD::ADDE: in ExpandIntegerResult()
1449 Hi = DAG.getNode(ISD::ADDE, DL, VTList, HiOps); in ExpandShiftByConstant()
1700 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps); in ExpandIntRes_ADDSUB()
1749 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps); in ExpandIntRes_ADDSUBC()
|
| H A D | SelectionDAG.cpp | 2253 case ISD::ADDE: { in computeKnownBits()
3496 case ISD::ADDE: in getNode()
|
| H A D | DAGCombiner.cpp | 1276 case ISD::ADDE: return visitADDE(N); in visit()
1760 return DAG.getNode(ISD::ADDE, SDLoc(N), N->getVTList(), in visitADDE()
|
| /minix/external/bsd/llvm/dist/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1462 setOperationAction(ISD::ADDE, MVT::i64, Custom); in SparcTargetLowering()
2697 case ISD::ADDC: hiOpc = ISD::ADDE; break; in LowerADDC_ADDE_SUBC_SUBE()
2698 case ISD::ADDE: hasChain = true; break; in LowerADDC_ADDE_SUBC_SUBE()
2832 case ISD::ADDE: in LowerOperation()
|
| H A D | SparcInstrInfo.td | 523 defm ADDE : F3_12<"addxcc", 0b011000, adde, IntRegs, i32, simm13Op>;
|
| /minix/external/bsd/llvm/dist/llvm/lib/Target/R600/ |
| H A D | SIISelLowering.cpp | 71 setOperationAction(ISD::ADDE, MVT::i32, Legal); in SITargetLowering()
830 SDValue Hi = DAG.getNode(ISD::ADDE, DL, DAG.getVTList(MVT::i32, MVT::Glue), in LowerGlobalAddress()
|
| H A D | R600ISelLowering.cpp | 187 setOperationAction(ISD::ADDE, VT, Expand); in R600TargetLowering()
|
| H A D | AMDGPUISelLowering.cpp | 331 setOperationAction(ISD::ADDE, VT, Expand); in AMDGPUTargetLowering()
|
| /minix/external/bsd/llvm/dist/llvm/lib/Target/XCore/ |
| H A D | XCoreISelLowering.cpp | 96 setOperationAction(ISD::ADDE, MVT::i32, Expand); in XCoreTargetLowering()
|
| /minix/external/bsd/llvm/dist/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 355 def adde : SDNode<"ISD::ADDE" , SDTIntBinOp,
|
| /minix/external/bsd/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 226 setOperationAction(ISD::ADDE, MVT::i32, Custom); in AArch64TargetLowering()
230 setOperationAction(ISD::ADDE, MVT::i64, Custom); in AArch64TargetLowering()
1437 case ISD::ADDE: in LowerADDC_ADDE_SUBC_SUBE()
1911 case ISD::ADDE: in LowerOperation()
|
| /minix/external/bsd/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 335 case ISD::ADDE: in IsProfitableToFold()
|
| H A D | X86ISelLowering.cpp | 441 setOperationAction(ISD::ADDE, VT, Custom); in resetOperationActions()
19551 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break; in LowerADDC_ADDE_SUBC_SUBE()
19697 case ISD::ADDE: in LowerOperation()
19734 case ISD::ADDE: in ReplaceNodeResults()
|
| /minix/external/bsd/llvm/dist/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 232 setOperationAction(ISD::ADDE, MVT::i64, Expand); in NVPTXTargetLowering()
|
| /minix/external/bsd/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.td | 2255 defm ADDE : XOForm_1rc<31, 138, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
|