/minix/external/bsd/llvm/dist/llvm/test/CodeGen/R600/ |
H A D | local-64.ll | 5 ; BOTH: ds_read_b32 [[REG:v[0-9]+]], v{{[0-9]+}} offset:28 [M0] 15 ; BOTH: ds_read_b32 [[REG:v[0-9]+]], v{{[0-9]+}} [M0] 25 ; BOTH: ds_read_u8 [[REG:v[0-9]+]], {{v[0-9]+}} offset:65535 [M0] 40 ; BOTH: ds_read_u8 [[REG:v[0-9]+]], [[VREGADDR]] [M0] 51 ; BOTH: ds_read_b64 [[REG:v[[0-9]+:[0-9]+]]], v{{[0-9]+}} offset:56 [M0] 61 ; BOTH: ds_read_b64 [[REG:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}} [M0] 81 ; BOTH: ds_read_b64 [[REG:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}} [M0] 100 ; BOTH: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} [M0] 116 ; BOTH: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} [M0] 135 ; BOTH-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} [M0] [all …]
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H A D | atomic_cmp_swap_local.ll | 10 ; SI: ds_cmpst_rtn_b32 [[RESULT:v[0-9]+]], [[VPTR]], [[VCMP]], [[VSWAP]] offset:16 [M0] 28 …, [[VPTR]], v{{\[}}[[LOVCMP]]:[[HIVCMP]]{{\]}}, v{{\[}}[[LOSWAPV]]:[[HISWAPV]]{{\]}} offset:32 [M0] 41 ; CI: ds_cmpst_rtn_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16 [M0] 59 ; SI: ds_cmpst_b32 [[VPTR]], [[VCMP]], [[VSWAP]] offset:16 [M0] 76 …4 [[VPTR]], v{{\[}}[[LOVCMP]]:[[HIVCMP]]{{\]}}, v{{\[}}[[LOSWAPV]]:[[HISWAPV]]{{\]}} offset:32 [M0]
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H A D | local-memory-two-objects.ll | 33 ; SI: ds_read_b32 {{v[0-9]+}}, [[SIPTR]] [M0] 34 ; CI: ds_read_b32 {{v[0-9]+}}, [[ADDRR:v[0-9]+]] offset:16 [M0] 35 ; CI: ds_read_b32 {{v[0-9]+}}, [[ADDRR]] [M0]
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H A D | local-atomics.ll | 10 ; SI: ds_wrxchg_rtn_b32 [[RESULT:v[0-9]+]], [[VPTR]], [[DATA]] [M0] 36 ; SI: ds_add_rtn_u32 [[RESULT:v[0-9]+]], [[VPTR]], [[DATA]] [M0] 58 ; SI: ds_add_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} [M0] 73 ; SI: ds_inc_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, [[NEGONE]] [M0] 95 ; SI: ds_inc_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} [M0] 131 ; SI: ds_dec_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, [[NEGONE]] [M0] 310 ; SI: ds_wrxchg_rtn_b32 [[RESULT:v[0-9]+]], [[VPTR]], [[DATA]] [M0] 331 ; SI: ds_add_u32 [[VPTR]], [[DATA]] [M0] 348 ; SI: ds_add_u32 v{{[0-9]+}}, v{{[0-9]+}} [M0] 349 ; CI: ds_add_u32 v{{[0-9]+}}, v{{[0-9]+}} offset:16 [M0] [all …]
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H A D | ds_write2st64.ll | 10 ; SI: ds_write2st64_b32 [[VPTR]], [[VAL]], [[VAL]] offset0:0 offset1:1 [M0] 28 ; SI: ds_write2st64_b32 [[VPTR]], [[VAL0]], [[VAL1]] offset0:2 offset1:5 [M0] 49 ; SI: ds_write2st64_b32 [[VPTR]], [[VAL0]], [[VAL1]] offset0:0 offset1:255 [M0] 69 ; SI: ds_write2st64_b64 [[VPTR]], [[VAL0]], [[VAL1]] offset0:4 offset1:127 [M0]
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H A D | ds_write2.ll | 10 ; SI: ds_write2_b32 [[VPTR]], [[VAL]], [[VAL]] offset0:0 offset1:8 [M0] 28 ; SI: ds_write2_b32 [[VPTR]], [[VAL0]], [[VAL1]] offset0:0 offset1:8 [M0] 87 ; SI: ds_write2_b32 [[VPTR]], v[[VAL0]], v[[VAL1]] offset0:0 offset1:8 [M0] 108 ; SI: ds_write2_b32 [[VPTR]], v[[VAL0]], v[[VAL1]] offset0:0 offset1:8 [M0] 127 ; SI: ds_write2_b32 [[VPTR]], v[[VAL0]], v[[VAL1]] offset0:0 offset1:8 [M0] 147 ; SI: ds_write2_b32 [[VPTR]], [[VAL0]], [[VAL1]] offset0:0 offset1:255 [M0] 271 ; SI: ds_write2_b64 [[VPTR]], [[VAL]], [[VAL]] offset0:0 offset1:8 [M0] 288 ; SI: ds_write2_b32 [[VPTR]], v[[VAL0]], v[[VAL1]] offset0:0 offset1:1 [M0] 289 ; SI: ds_write2_b32 [[VPTR]], v[[VAL0]], v[[VAL1]] offset0:14 offset1:15 [M0] 307 ; SI: ds_write2_b64 [[VPTR]], [[VAL0]], [[VAL1]] offset0:0 offset1:8 [M0]
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H A D | shl_add_ptr.ll | 20 ; SI: ds_read_b32 {{v[0-9]+}}, [[PTR]] offset:8 [M0] 37 ; SI: ds_read_b32 [[RESULT:v[0-9]+]], [[PTR]] offset:8 [M0] 74 ; SI-NEXT: ds_read2st64_b32 {{v\[[0-9]+:[0-9]+\]}}, [[PTR]] offset0:1 offset1:9 [M0] 90 ; SI: ds_write_b32 [[PTR]], {{v[0-9]+}} offset:8 [M0]
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H A D | 32-bit-local-address-space.ll | 134 ; SI: ds_write_b32 [[VPTR]], v{{[0-9]+}} [M0]{{$}}
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/minix/external/bsd/llvm/dist/llvm/test/CodeGen/ARM/ |
H A D | atomic-op.ll | 33 ; CHECK-M0: bl ___sync_fetch_and_add_4 42 ; CHECK-M0: bl ___sync_fetch_and_sub_4 51 ; CHECK-M0: bl ___sync_fetch_and_add_4 60 ; CHECK-M0: bl ___sync_fetch_and_sub_4 69 ; CHECK-M0: bl ___sync_fetch_and_and_4 78 ; CHECK-M0: bl ___sync_fetch_and_or_4 343 ; CHECK-M0: ___sync_lock_test_and_set 344 ; CHECK-M0: ___sync_lock_test_and_set 364 ; CHECK-M0: ldr [[R0:r[0-9]]], [r0] 365 ; CHECK-M0: dmb [all …]
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H A D | build-attributes.ll | 694 ; CORTEX-M0: .cpu cortex-m0 695 ; CORTEX-M0: .eabi_attribute 6, 12 696 ; CORTEX-M0-NOT: .eabi_attribute 7 697 ; CORTEX-M0: .eabi_attribute 8, 0 698 ; CORTEX-M0: .eabi_attribute 9, 1 701 ; CORTEX-M0: .eabi_attribute 20, 1 702 ; CORTEX-M0: .eabi_attribute 21, 1 704 ; CORTEX-M0: .eabi_attribute 23, 3 705 ; CORTEX-M0: .eabi_attribute 24, 1 706 ; CORTEX-M0: .eabi_attribute 25, 1 [all …]
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/minix/external/bsd/llvm/dist/llvm/include/llvm/Support/ |
H A D | CommandLine.h | 1187 apply(M0, this); 1195 apply(M0, this); 1204 apply(M0, this); 1213 apply(M0, this); 1223 apply(M0, this); 1235 apply(M0, this); 1249 apply(M0, this); 1264 apply(M0, this); 1381 apply(M0, this); 1388 apply(M0, this); [all …]
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/minix/external/bsd/llvm/dist/llvm/unittests/Support/ |
H A D | CommandLineTest.cpp | 51 explicit StackOption(const M0t &M0) : Base(M0) {} in StackOption() argument 55 StackOption(const M0t &M0, const M1t &M1) : Base(M0, M1) {} in StackOption() argument 59 StackOption(const M0t &M0, const M1t &M1, const M2t &M2) : Base(M0, M1, M2) {} in StackOption() argument 63 StackOption(const M0t &M0, const M1t &M1, const M2t &M2, const M3t &M3) in StackOption() argument 64 : Base(M0, M1, M2, M3) {} in StackOption()
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/minix/crypto/external/bsd/openssl/dist/crypto/md5/asm/ |
H A D | md5-ia64.S | 125 #define M0 in4 macro 542 G(A, B, C, D, M0) \ 543 COMPUTE(A, B, 5, M0, RotateM0) \ 552 H(A, B, C, D, M0) \ 562 I(A, B, C, D, M0) \ 666 mov Z = M0 677 mov M0 = M1 719 mov Z = M0 730 mov M0 = M4 772 mov Z = M0 [all …]
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/minix/external/bsd/llvm/dist/llvm/lib/Target/R600/ |
H A D | SILowerControlFlow.cpp | 338 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_ADD_I32), AMDGPU::M0) in LoadM0() 342 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0) in LoadM0() 361 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0) in LoadM0() 366 .addReg(AMDGPU::M0) in LoadM0() 374 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_ADD_I32), AMDGPU::M0) in LoadM0() 375 .addReg(AMDGPU::M0) in LoadM0() 441 .addReg(AMDGPU::M0, RegState::Implicit) in IndirectSrc() 463 .addReg(AMDGPU::M0, RegState::Implicit) in IndirectDst()
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H A D | SIRegisterInfo.td | 40 def M0 : SIReg <"M0", 124>; 172 // Special register classes for predicates and the M0 register 180 def M0Reg : RegisterClass<"AMDGPU", [i32], 32, (add M0)>;
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H A D | SIRegisterInfo.cpp | 246 bool isM0 = SubReg == AMDGPU::M0; in eliminateFrameIndex() 265 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0) in eliminateFrameIndex()
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H A D | SIInsertWaits.cpp | 432 if (Op.isReg() && Op.isDef() && Op.getReg() == AMDGPU::M0) in handleSendMsg()
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H A D | SIInstrInfo.td | 1497 asm#" $vdst, $addr"#"$offset"#" [M0]", 1519 asm#" $vdst, $addr"#"$offset0"#"$offset1 [M0]", 1540 asm#" $addr, $data0"#"$offset"#" [M0]", 1562 asm#" $addr, $data0, $data1"#"$offset0"#"$offset1 [M0]", 1586 asm#" $vdst, $addr, $data0"#"$offset"#" [M0]", [], noRetOp>; 1607 asm#" $vdst, $addr, $data0, $data1"#"$offset"#" [M0]", 1627 asm#" $addr, $data0, $data1"#"$offset"#" [M0]", 1649 asm#" $addr, $data0"#"$offset"#" [M0]", 1962 asm#" $data, $addr, [M0, FLAT_SCRATCH]", []> { 1971 name#" $data, $addr, [M0, FLAT_SCRATCH]",
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/minix/external/bsd/llvm/dist/llvm/lib/Target/Hexagon/ |
H A D | HexagonRegisterInfo.td | 116 // C6 and C7 can also be M0 and M1, but register names must be unique, even 118 def M0 : Mx<0, "m0">, DwarfRegNum<[72]>; 134 def C6 : Rc<6, "c6", [], [M0]>, DwarfRegNum<[72]>; 183 def ModRegs : RegisterClass<"Hexagon", [i32], 32, (add M0, M1)>; 189 M0, M1, C6, C7, CS0, CS1, UPCL, UPCH, 200 M0, M1,
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/minix/external/bsd/llvm/dist/llvm/test/CodeGen/Thumb/ |
H A D | 2012-04-26-M0ISelBug.ll | 2 ; Cortex-M0 doesn't have 32-bit Thumb2 instructions (except for dmb, mrs, etc.)
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/minix/external/bsd/llvm/dist/llvm/unittests/Analysis/ |
H A D | ScalarEvolutionTest.cpp | 64 const SCEVMulExpr *M0 = cast<SCEVMulExpr>(P0); in TEST_F() local 68 EXPECT_EQ(cast<SCEVConstant>(M0->getOperand(0))->getValue()->getZExtValue(), in TEST_F() 76 EXPECT_EQ(cast<SCEVUnknown>(M0->getOperand(1))->getValue(), V0); in TEST_F() 85 EXPECT_EQ(cast<SCEVUnknown>(M0->getOperand(1))->getValue(), V0); in TEST_F()
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/minix/external/bsd/llvm/dist/llvm/test/CodeGen/X86/ |
H A D | shuffle-combine-crash.ll | 5 ; (shuffle (shuffle A, Undef, M0), Undef, M1) -> (shuffle A, Undef, M2)
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H A D | swizzle-avx2.ll | 5 ; shuffle (shuffle (x, undef, M0), undef, M1) -> shuffle(x, undef, M2)
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/minix/external/bsd/llvm/dist/llvm/lib/Target/Hexagon/Disassembler/ |
H A D | HexagonDisassembler.cpp | 113 Register = Hexagon::M0; in DecodeModRegsRegisterClass()
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/minix/external/bsd/llvm/dist/llvm/lib/Transforms/InstCombine/ |
H A D | InstCombineMulDivRem.cpp | 586 Value *M0 = isNormalFp(cast<Constant>(M1)) ? in visitFMul() local 589 if (M0 && M1) { in visitFMul() 591 std::swap(M0, M1); in visitFMul() 594 ? BinaryOperator::CreateFAdd(M0, M1) in visitFMul() 595 : BinaryOperator::CreateFSub(M0, M1); in visitFMul()
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