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Searched refs:MRM2r (Results 1 – 16 of 16) sorted by relevance

/minix/external/bsd/llvm/dist/llvm/lib/Target/X86/MCTargetDesc/
H A DX86BaseInfo.h296 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, // Format /0 /1 /2 /3 enumerator
685 case X86II::MRM2r: case X86II::MRM3r: in getMemoryOperandNo()
H A DX86MCCodeEmitter.cpp899 case X86II::MRM2r: case X86II::MRM3r: in EmitVEXOpcodePrefix()
1397 case X86II::MRM2r: case X86II::MRM3r: in EncodeInstruction()
/minix/external/bsd/llvm/dist/llvm/lib/Target/X86/
H A DX86InstrShiftRotate.td343 def RCL8r1 : I<0xD0, MRM2r, (outs GR8:$dst), (ins GR8:$src1),
345 def RCL8ri : Ii8<0xC0, MRM2r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$cnt),
348 def RCL8rCL : I<0xD2, MRM2r, (outs GR8:$dst), (ins GR8:$src1),
351 def RCL16r1 : I<0xD1, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
353 def RCL16ri : Ii8<0xC1, MRM2r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$cnt),
356 def RCL16rCL : I<0xD3, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
359 def RCL32r1 : I<0xD1, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
361 def RCL32ri : Ii8<0xC1, MRM2r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$cnt),
364 def RCL32rCL : I<0xD3, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
368 def RCL64r1 : RI<0xD1, MRM2r, (outs GR64:$dst), (ins GR64:$src1),
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H A DX86InstrControl.td189 def CALL16r : I<0xFF, MRM2r, (outs), (ins GR16:$dst),
197 def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst),
268 def CALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst),
H A DX86InstrMMX.td446 defm MMX_PSRLW : MMXI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
449 defm MMX_PSRLD : MMXI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
452 defm MMX_PSRLQ : MMXI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
H A DX86InstrFPStack.td262 def COM_FST0r : FPST0rInst <MRM2r, "fcom\t$op">;
355 def CMOVBE_F : FPI<0xDA, MRM2r, (outs RST:$op), (ins),
363 def CMOVNBE_F: FPI<0xDB, MRM2r, (outs RST:$op), (ins),
510 def ST_Frr : FPI<0xDD, MRM2r, (outs), (ins RST:$op), "fst\t$op", IIC_FST>;
H A DX86InstrSystem.td431 def LLDT16r : I<0x00, MRM2r, (outs), (ins GR16:$src),
537 def WRFSBASE : I<0xAE, MRM2r, (outs), (ins GR32:$src),
540 def WRFSBASE64 : RI<0xAE, MRM2r, (outs), (ins GR64:$src),
H A DX86InstrArithmetic.td420 def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src1),
423 def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
426 def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
429 def NOT64r : RI<0xF7, MRM2r, (outs GR64:$dst), (ins GR64:$src1), "not{q}\t$dst",
1198 defm ADC : ArithBinOp_RFF<0x10, 0x12, 0x14, "adc", MRM2r, MRM2m, X86adc_flag,
H A DX86InstrSSE.td4323 defm VPSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
4326 defm VPSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
4329 defm VPSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
4369 defm VPSRLWY : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
4372 defm VPSRLDY : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
4375 defm VPSRLQY : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
4415 defm PSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "psrlw", X86vsrl, X86vsrli,
4418 defm PSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "psrld", X86vsrl, X86vsrli,
4421 defm PSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "psrlq", X86vsrl, X86vsrli,
H A DX86InstrInfo.td2095 defm BLSMSK32 : bmi_bls<"blsmsk{l}", MRM2r, MRM2m, GR32, i32mem>;
2096 defm BLSMSK64 : bmi_bls<"blsmsk{q}", MRM2r, MRM2m, GR64, i64mem>, VEX_W;
2314 defm BLSFILL : tbm_binary_intr<0x01, "blsfill", MRM2r, MRM2m>;
H A DX86InstrFormats.td30 def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>;
H A DX86InstrAVX512.td3362 defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,
3365 defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,
/minix/external/bsd/llvm/dist/llvm/utils/TableGen/
H A DX86RecognizableInstr.cpp97 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, enumerator
707 case X86Local::MRM2r: in emitInstructionSpecifier()
845 case X86Local::MRM2r: case X86Local::MRM3r: in emitDecodePath()
/minix/external/bsd/llvm/dist/llvm/test/TableGen/
H A DTargetInstrInfo.td52 def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>;
/minix/external/bsd/llvm/dist/llvm/docs/TableGen/
H A DLangIntro.rst547 def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst, variable_ops),
/minix/external/bsd/llvm/dist/llvm/docs/
H A DWritingAnLLVMBackend.rst1821 case X86II::MRM2r: case X86II::MRM3r: // a REGISTER r/m operand and