/minix/external/bsd/llvm/dist/llvm/test/CodeGen/R600/ |
H A D | load.ll | 25 ; R600: 24 27 ; R600: 24 54 ; R600-DAG: 24 56 ; R600-DAG: 24 136 ; R600: 16 138 ; R600: 16 282 ; R600: 31 360 ; R600: 24 362 ; R600: 24 401 ; R600: 16 [all …]
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H A D | llvm.sqrt.ll | 5 ; R600-LABEL: {{^}}sqrt_f32: 6 ; R600: RECIPSQRT_CLAMPED * T{{[0-9]\.[XYZW]}}, KC0[2].Z 7 ; R600: MUL NON-IEEE T{{[0-9]\.[XYZW]}}, KC0[2].Z, PS 17 ; R600-LABEL: {{^}}sqrt_v2f32: 19 ; R600-DAG: MUL NON-IEEE T{{[0-9]\.[XYZW]}}, KC0[2].W, PS 21 ; R600-DAG: MUL NON-IEEE T{{[0-9]\.[XYZW]}}, KC0[3].X, PS 32 ; R600-LABEL: {{^}}sqrt_v4f32: 34 ; R600-DAG: MUL NON-IEEE T{{[0-9]\.[XYZW]}}, KC0[3].Y, PS 36 ; R600-DAG: MUL NON-IEEE T{{[0-9]\.[XYZW]}}, KC0[3].Z, PS 38 ; R600-DAG: MUL NON-IEEE T{{[0-9]\.[XYZW]}}, KC0[3].W, PS [all …]
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H A D | build_vector.ll | 1 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600 5 ; R600: {{^}}build_vector2: 6 ; R600: MOV 7 ; R600: MOV 8 ; R600-NOT: MOV 19 ; R600: {{^}}build_vector4: 20 ; R600: MOV 21 ; R600: MOV 22 ; R600: MOV 23 ; R600: MOV [all …]
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H A D | fadd.ll | 6 ; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, KC0[2].W 26 ; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 27 ; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 44 ; R600: ADD 45 ; R600: ADD 46 ; R600: ADD 47 ; R600: ADD 48 ; R600: ADD 49 ; R600: ADD 50 ; R600: ADD [all …]
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H A D | fdiv.ll | 1 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 %s 10 ; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[3].Z 11 ; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[3].Y 12 ; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[3].X, PS 13 ; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].W, PS 27 ; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[3].Z 28 ; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[3].Y 44 ; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 45 ; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 46 ; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} [all …]
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H A D | 128bit-kernel-args.ll | 1 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600 5 ; R600: {{^}}v4i32_kernel_arg: 6 ; R600-DAG: MOV {{[* ]*}}T[[GPR:[0-9]]].X, KC0[3].Y 7 ; R600-DAG: MOV {{[* ]*}}T[[GPR]].Y, KC0[3].Z 8 ; R600-DAG: MOV {{[* ]*}}T[[GPR]].Z, KC0[3].W 9 ; R600-DAG: MOV {{[* ]*}}T[[GPR]].W, KC0[4].X 18 ; R600: {{^}}v4f32_kernel_arg: 19 ; R600-DAG: MOV {{[* ]*}}T[[GPR:[0-9]]].X, KC0[3].Y 20 ; R600-DAG: MOV {{[* ]*}}T[[GPR]].Y, KC0[3].Z 21 ; R600-DAG: MOV {{[* ]*}}T[[GPR]].Z, KC0[3].W [all …]
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H A D | setcc.ll | 38 ; R600: SETE_DX10 49 ; R600: SETGT_DX10 60 ; R600: SETGE_DX10 71 ; R600: SETGT_DX10 143 ; R600: SETGE 144 ; R600: SETE_DX10 156 ; R600: SETGT 170 ; R600: SETGE 184 ; R600: SETGT 211 ; R600: OR_INT [all …]
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H A D | llvm.floor.ll | 1 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK 4 ; R600-CHECK: {{^}}f32: 5 ; R600-CHECK: FLOOR 15 ; R600-CHECK: {{^}}v2f32: 16 ; R600-CHECK: FLOOR 17 ; R600-CHECK: FLOOR 28 ; R600-CHECK: {{^}}v4f32: 29 ; R600-CHECK: FLOOR 30 ; R600-CHECK: FLOOR 31 ; R600-CHECK: FLOOR [all …]
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H A D | llvm.round.ll | 1 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck %s --check-prefix=R600 --check-prefix=FUNC 4 ; R600: FRACT {{.*}}, [[ARG:KC[0-9]\[[0-9]+\]\.[XYZW]]] 5 ; R600-DAG: ADD {{.*}}, -0.5 6 ; R600-DAG: CEIL {{.*}} [[ARG]] 7 ; R600-DAG: FLOOR {{.*}} [[ARG]] 8 ; R600-DAG: CNDGE 9 ; R600-DAG: CNDGT 10 ; R600: CNDGE {{[^,]+}}, [[ARG]] 24 ; R600: CF_END 33 ; R600: CF_END
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H A D | fneg.ll | 2 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s 5 ; R600: -PV 15 ; R600: -PV 16 ; R600: -PV 27 ; R600: -PV 28 ; R600: -T 29 ; R600: -PV 30 ; R600: -PV 47 ; R600-NOT: XOR 48 ; R600: -KC0[2].Z
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H A D | uint_to_fp.ll | 3 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s 6 ; R600-DAG: UINT_TO_FLT * T{{[0-9]+\.[XYZW]}}, KC0[2].Z 17 ; R600-DAG: UINT_TO_FLT * T{{[0-9]+\.[XYZW]}}, KC0[2].W 18 ; R600-DAG: UINT_TO_FLT * T{{[0-9]+\.[XYZW]}}, KC0[3].X 30 ; R600: UINT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 31 ; R600: UINT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 32 ; R600: UINT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 33 ; R600: UINT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 48 ; R600: UINT_TO_FLT 49 ; R600: UINT_TO_FLT [all …]
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H A D | llvm.rint.ll | 1 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck %s -check-prefix=R600 -check-prefix=FUNC 6 ; R600: RNDNE 17 ; R600: RNDNE 18 ; R600: RNDNE 30 ; R600: RNDNE 31 ; R600: RNDNE 32 ; R600: RNDNE 33 ; R600: RNDNE 47 ; R600: RNDNE
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H A D | fabs.ll | 10 ; R600-NOT: AND 11 ; R600: |PV.{{[XYZW]}}| 23 ; R600-NOT: AND 24 ; R600: |PV.{{[XYZW]}}| 36 ; R600: |{{(PV|T[0-9])\.[XYZW]}}| 46 ; R600: |{{(PV|T[0-9])\.[XYZW]}}| 47 ; R600: |{{(PV|T[0-9])\.[XYZW]}}| 58 ; R600: |{{(PV|T[0-9])\.[XYZW]}}| 59 ; R600: |{{(PV|T[0-9])\.[XYZW]}}| 60 ; R600: |{{(PV|T[0-9])\.[XYZW]}}| [all …]
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H A D | bfi_int.ll | 1 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=R600 %s 8 ; R600: {{^}}bfi_def: 9 ; R600: BFI_INT 24 ; R600: {{^}}bfi_sha256_ch: 25 ; R600: BFI_INT 39 ; R600: {{^}}bfi_sha256_ma: 40 ; R600: XOR_INT * [[DST:T[0-9]+\.[XYZW]]], KC0[2].Z, KC0[2].W 41 ; R600: BFI_INT * {{T[0-9]+\.[XYZW]}}, {{[[DST]]|PV\.[XYZW]}}, KC0[3].X, KC0[2].W
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H A D | rotr.ll | 1 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck --check-prefix=R600 -check-prefix=FUNC %s 6 ; R600: BIT_ALIGN_INT 20 ; R600: BIT_ALIGN_INT 21 ; R600: BIT_ALIGN_INT 36 ; R600: BIT_ALIGN_INT 37 ; R600: BIT_ALIGN_INT 38 ; R600: BIT_ALIGN_INT 39 ; R600: BIT_ALIGN_INT
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H A D | r600-encoding.ll | 2 ; RUN: llc < %s -march=r600 -show-mc-encoding -mcpu=rs880 | FileCheck --check-prefix=R600 %s 4 ; The earliest R600 GPUs have a slightly different encoding than the rest of 10 ; R600: {{^}}test: 11 ; R600: MUL_IEEE {{[ *TXYZWPVxyzw.,0-9]+}} ; encoding: [{{0x[0-9a-f]+,0x[0-9a-f]+,0x[0-9a-f]+,0x[0-… 19 call void @llvm.R600.store.swizzle(<4 x float> %vec, i32 0, i32 0) 23 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
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H A D | fmul.ll | 3 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s 7 ; R600: MUL_IEEE {{\** *}}{{T[0-9]+\.[XYZW]}}, KC0[2].Z, KC0[2].W 17 declare float @llvm.R600.load.input(i32) readnone 22 ; R600: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}} 23 ; R600: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}} 35 ; R600: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 36 ; R600: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 37 ; R600: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 38 ; R600: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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H A D | texture-input-merge.ll | 19 …%14 = call <4 x float> @llvm.R600.tex(<4 x float> %10, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i… 20 …%15 = call <4 x float> @llvm.R600.tex(<4 x float> %12, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i… 21 …%16 = call <4 x float> @llvm.R600.tex(<4 x float> %13, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i… 24 call void @llvm.R600.store.swizzle(<4 x float> %18, i32 0, i32 0) 28 declare <4 x float> @llvm.R600.tex(<4 x float>, i32, i32, i32, i32, i32, i32, i32, i32, i32) readno… 29 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
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H A D | sint_to_fp.ll | 3 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s 7 ; R600: INT_TO_FLT * T{{[0-9]+\.[XYZW]}}, KC0[2].Z 16 ; R600-DAG: INT_TO_FLT * T{{[0-9]+\.[XYZW]}}, KC0[2].W 17 ; R600-DAG: INT_TO_FLT * T{{[0-9]+\.[XYZW]}}, KC0[3].X 28 ; R600: INT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 29 ; R600: INT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 30 ; R600: INT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 31 ; R600: INT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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H A D | call_fs.ll | 3 ; RUN: llc < %s -march=r600 -mcpu=rv710 -show-mc-encoding -o - | FileCheck --check-prefix=R600 %s 8 ; R600: {{^}}call_fs: 9 ; R600: .long 257 10 ; R600:CALL_FS ; encoding: [0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x89]
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H A D | tex-clause-antidep.ll | 15 …%9 = call <4 x float> @llvm.R600.tex(<4 x float> %8, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32… 16 …%10 = call <4 x float> @llvm.R600.tex(<4 x float> %8, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i3… 18 call void @llvm.R600.store.swizzle(<4 x float> %11, i32 0, i32 0) 22 declare <4 x float> @llvm.R600.tex(<4 x float>, i32, i32, i32, i32, i32, i32, i32, i32, i32) readno… 23 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
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H A D | fsub.ll | 1 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s 18 ; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, -KC0[2].W 27 declare float @llvm.R600.load.input(i32) readnone 32 ; R600-DAG: ADD {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[3].X, -KC0[3].Z 33 ; R600-DAG: ADD {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].W, -KC0[3].Y 45 ; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}} 46 ; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}} 47 ; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}} 48 ; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}}
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H A D | fneg-fabs.ll | 3 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s 33 ; R600-NOT: AND 34 ; R600: |PV.{{[XYZW]}}| 35 ; R600: -PV 48 ; R600-NOT: AND 49 ; R600: |PV.{{[XYZW]}}| 50 ; R600: -PV 83 ; R600: |{{(PV|T[0-9])\.[XYZW]}}| 84 ; R600: -PV 85 ; R600: |{{(PV|T[0-9])\.[XYZW]}}| [all …]
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H A D | atomic_load_add.ll | 3 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s 6 ; R600: LDS_ADD * 14 ; R600: LDS_ADD * 23 ; R600: LDS_ADD_RET * 32 ; R600: LDS_ADD_RET *
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H A D | llvm.AMDGPU.imad24.ll | 4 ; RUN: llc -march=r600 -mcpu=redwood -verify-machineinstrs < %s | FileCheck -check-prefix=R600 -che… 5 ; XUN: llc -march=r600 -mcpu=r600 -verify-machineinstrs < %s | FileCheck -check-prefix=R600 -check-… 6 ; XUN: llc -march=r600 -mcpu=r770 -verify-machineinstrs < %s | FileCheck -check-prefix=R600 -check-… 15 ; R600: MULLO_INT 16 ; R600: ADD_INT
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