| /minix/external/bsd/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 787 SETULE, // 1 1 0 1 True if unordered, less than, or equal enumerator
812 return Code == SETUGT || Code == SETUGE || Code == SETULT || Code == SETULE; in isUnsignedIntSetCC()
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| /minix/external/bsd/llvm/dist/llvm/lib/CodeGen/ |
| H A D | Analysis.cpp | 176 case FCmpInst::FCMP_ULE: return ISD::SETULE; in getFCmpCondCode()
188 case ISD::SETOLE: case ISD::SETULE: return ISD::SETLE; in getFCmpCodeWithoutNaN()
203 case ICmpInst::ICMP_ULE: return ISD::SETULE; in getICmpCondCode()
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| /minix/external/bsd/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonSelectCCInfo.td | 54 IntRegs:$fval, SETULE)),
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| /minix/external/bsd/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | TargetLowering.cpp | 187 case ISD::SETULE: in softenSetCCOperands()
1412 case ISD::SETULE: in SimplifySetCC()
1434 case ISD::SETULE: { in SimplifySetCC()
1593 if (Cond == ISD::SETLE || Cond == ISD::SETULE) { in SimplifySetCC()
1614 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal) in SimplifySetCC()
1701 Cond == ISD::SETULE || Cond == ISD::SETUGT) { in SimplifySetCC()
1702 bool AdjOne = (Cond == ISD::SETULE || Cond == ISD::SETUGT); in SimplifySetCC()
1713 NewCond = (Cond == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE; in SimplifySetCC()
1771 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE); in SimplifySetCC()
1995 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y in SimplifySetCC()
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| H A D | SelectionDAGDumper.cpp | 316 case ISD::SETULE: return "setule"; in getOperationName()
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| H A D | LegalizeIntegerTypes.cpp | 910 case ISD::SETULE: in PromoteSetCCOperands()
2663 case ISD::SETULE: LowCC = ISD::SETULE; break; in IntegerExpandSetCCOperands()
2698 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) || in IntegerExpandSetCCOperands()
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| H A D | SelectionDAG.cpp | 293 case ISD::SETULE: in isSignedOp()
1828 case ISD::SETULE: return getConstant(C1.ule(C2), VT); in FoldSetCC()
1878 case ISD::SETULE: return getConstant(R!=APFloat::cmpGreaterThan, VT); in FoldSetCC()
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| H A D | LegalizeDAG.cpp | 1705 case ISD::SETULE: in LegalizeSetCCCondCode()
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| H A D | SelectionDAGBuilder.cpp | 1697 DAG.getConstant(High-Low, VT), ISD::SETULE); in visitSwitchCase()
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| /minix/external/bsd/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelDAGToDAG.cpp | 2056 case ISD::SETULE: in getPredicateForSetCC()
2086 case ISD::SETULE: in getCRIdxForSetCC()
2117 case ISD::SETUGE: CC = ISD::SETULE; Swap = true; break; in getVCmpInst()
2125 case ISD::SETULE: CC = ISD::SETOGT; Negate = true; break; in getVCmpInst()
2161 case ISD::SETUGE: CC = ISD::SETULE; Swap = true; break; in getVCmpInst()
2170 case ISD::SETULE: CC = ISD::SETUGT; Negate = true; break; in getVCmpInst()
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| H A D | PPCInstrInfo.td | 2650 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULE)),
2838 defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULE)),
2866 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETULE)),
2906 defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULE)),
2934 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETULE)),
2961 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETULE)),
2992 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETULE)),
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| /minix/external/bsd/llvm/dist/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelLowering.cpp | 962 case ISD::SETULE: in isLegalDSPCondCode()
1008 else if (CondCode == ISD::SETULT || CondCode == ISD::SETULE) in performVSELECTCombine()
1702 Op->getOperand(2), ISD::SETULE); in lowerINTRINSIC_WO_CHAIN()
1708 lowerMSASplatImm(Op, 2, DAG), ISD::SETULE); in lowerINTRINSIC_WO_CHAIN()
1810 Op->getOperand(2), ISD::SETULE); in lowerINTRINSIC_WO_CHAIN()
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| H A D | MipsDSPInstrInfo.td | 1368 def : DSPSetCCPat<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETULE>;
1381 def : DSPSelectCCPat<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETULE>;
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| H A D | MipsMSAInstrInfo.td | 191 def vfsetule_v4f32 : vfsetcc_type<v4i32, v4f32, SETULE>;
192 def vfsetule_v2f64 : vfsetcc_type<v2i64, v2f64, SETULE>;
217 def vsetule_v16i8 : vsetcc_type<v16i8, SETULE>;
218 def vsetule_v8i16 : vsetcc_type<v8i16, SETULE>;
219 def vsetule_v4i32 : vsetcc_type<v4i32, SETULE>;
220 def vsetule_v2i64 : vsetcc_type<v2i64, SETULE>;
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| H A D | MipsISelLowering.cpp | 485 case ISD::SETULE: return Mips::FCOND_ULE; in condCodeToFCC()
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| /minix/external/bsd/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 1226 case ISD::SETULE: return ARMCC::LS; in IntCCToARMCC()
1253 case ISD::SETULE: CondCode = ARMCC::LE; break; in FPCCToARMCC()
3287 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT; in getARMCmp()
3298 case ISD::SETULE: in getARMCmp()
3301 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE; in getARMCmp()
3506 CC == ISD::SETULE) in checkVSELConstraints()
3516 if (CC == ISD::SETOLE || CC == ISD::SETULE || CC == ISD::SETOLT || in checkVSELConstraints()
4516 case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break; in LowerVSETCC()
4550 case ISD::SETULE: Swap = true; in LowerVSETCC()
9722 case ISD::SETULE: in PerformSELECT_CCCombine()
[all …]
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| /minix/external/bsd/llvm/dist/llvm/lib/Target/R600/ |
| H A D | AMDGPUInstructions.td | 114 def COND_ULE : PatLeaf <(cond), [{return N->get() == ISD::SETULE;}]>;
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| H A D | R600ISelLowering.cpp | 57 setCondCodeAction(ISD::SETULE, MVT::f32, Expand); in R600TargetLowering()
61 setCondCodeAction(ISD::SETULE, MVT::i32, Expand); in R600TargetLowering()
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| H A D | AMDGPUISelLowering.cpp | 1084 case ISD::SETULE: in CombineFMinMaxLegacy()
1147 case ISD::SETULE: in CombineIMinMax()
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| /minix/external/bsd/llvm/dist/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 528 def SETULT : CondCode; def SETULE : CondCode; def SETUNE : CondCode;
885 (setcc node:$lhs, node:$rhs, SETULE)>;
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| /minix/external/bsd/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 987 case ISD::SETULE: in changeIntCCToAArch64CC()
1043 case ISD::SETULE: in changeFPCCToAArch64CC()
1075 case ISD::SETULE: in changeVectorFPCCToAArch64CC()
1162 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT; in getAArch64Cmp()
1178 case ISD::SETULE: in getAArch64Cmp()
1184 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE; in getAArch64Cmp()
3734 case ISD::SETULE: in LowerSELECT_CC()
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| /minix/external/bsd/llvm/dist/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.cpp | 837 case ISD::SETULE: in EmitCMP()
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| /minix/external/bsd/llvm/dist/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1334 case ISD::SETULE: return SPCC::ICC_LEU; in IntCondCCodeToICC()
1358 case ISD::SETULE: return SPCC::FCC_ULE; in FPCondCCodeToFCC()
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| /minix/external/bsd/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 3792 case ISD::SETULE: return X86::COND_BE; in TranslateX86CC()
3836 case ISD::SETULE: in TranslateX86CC()
15254 case ISD::SETULE: Swap = true; // Fallthrough in translateX86FSETCC()
15325 case ISD::SETULE: Unsigned = true; //fall-through in LowerIntVSETCC_AVX512()
15455 case ISD::SETULE: Opc = X86ISD::PCMPGT; in LowerVSETCC()
15468 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break; in LowerVSETCC()
15500 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break; in LowerVSETCC()
23015 case ISD::SETULE: in matchIntegerMINMAX()
23033 case ISD::SETULE: in matchIntegerMINMAX()
23144 case ISD::SETULE: in PerformSELECTCombine()
[all …]
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| /minix/external/bsd/llvm/dist/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXVector.td | 976 (setcc node:$lhs, node:$rhs, SETULE)>;
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