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Searched refs:TB (Results 1 – 25 of 40) sorted by relevance

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/minix/external/bsd/llvm/dist/llvm/lib/Target/X86/
H A DX86InstrSystem.td19 TB;
60 IIC_SYS_ENTER_EXIT>, TB;
63 IIC_SYS_ENTER_EXIT>, TB;
248 [], IIC_INVLPG>, TB;
260 "ltr{w}\t$src", [], IIC_LTR>, TB;
262 "ltr{w}\t$src", [], IIC_LTR>, TB;
380 "verr\t$seg", [], IIC_VERR>, TB;
445 TB;
486 "xsave\t$dst", []>, TB;
490 "xrstor\t$dst", []>, TB;
[all …]
H A DX86InstrSVM.td19 def VMMCALL : I<0x01, MRM_D9, (outs), (ins), "vmmcall", []>, TB;
22 def STGI : I<0x01, MRM_DC, (outs), (ins), "stgi", []>, TB;
25 def CLGI : I<0x01, MRM_DD, (outs), (ins), "clgi", []>, TB;
29 def SKINIT : I<0x01, MRM_DE, (outs), (ins), "skinit\t{%eax|eax}", []>, TB;
34 "vmrun\t{%eax|eax}", []>, TB, Requires<[Not64BitMode]>;
37 "vmrun\t{%rax|rax}", []>, TB, Requires<[In64BitMode]>;
42 "vmload\t{%eax|eax}", []>, TB, Requires<[Not64BitMode]>;
45 "vmload\t{%rax|rax}", []>, TB, Requires<[In64BitMode]>;
50 "vmsave\t{%eax|eax}", []>, TB, Requires<[Not64BitMode]>;
53 "vmsave\t{%rax|rax}", []>, TB, Requires<[In64BitMode]>;
[all …]
H A DX86InstrExtension.td45 TB, OpSize16, Sched<[WriteALU]>;
49 TB, OpSize16, Sched<[WriteALULd]>;
66 OpSize32, TB, Sched<[WriteALULd]>;
71 TB, OpSize16, Sched<[WriteALU]>;
75 TB, OpSize16, Sched<[WriteALULd]>;
130 TB, Sched<[WriteALULd]>;
138 TB, Sched<[WriteALULd]>;
151 TB, Sched<[WriteALU]>;
154 TB, Sched<[WriteALULd]>;
157 TB, Sched<[WriteALU]>;
[all …]
H A DX86InstrVMX.td33 def VMCALL : I<0x01, MRM_C1, (outs), (ins), "vmcall", []>, TB;
37 def VMFUNC : I<0x01, MRM_D4, (outs), (ins), "vmfunc", []>, TB;
39 def VMLAUNCH : I<0x01, MRM_C2, (outs), (ins), "vmlaunch", []>, TB;
41 def VMRESUME : I<0x01, MRM_C3, (outs), (ins), "vmresume", []>, TB;
45 "vmptrst\t$vmcs", []>, TB;
63 def VMXOFF : I<0x01, MRM_C4, (outs), (ins), "vmxoff", []>, TB;
H A DX86InstrCMovSetCC.td25 IIC_CMOV16_RR>, TB, OpSize16;
31 IIC_CMOV32_RR>, TB, OpSize32;
37 IIC_CMOV32_RR>, TB;
47 TB, OpSize16;
53 TB, OpSize32;
58 CondNode, EFLAGS))], IIC_CMOV32_RM>, TB;
88 IIC_SET_R>, TB, Sched<[WriteALU]>;
92 IIC_SET_M>, TB, Sched<[WriteALU, WriteStore]>;
H A DX86InstrSGX.td20 "encls", []>, TB, Requires<[HasSGX]>;
24 "enclu", []>, TB, Requires<[HasSGX]>;
H A DX86InstrTSX.td34 "xend", [(int_x86_xend)]>, TB, Requires<[HasRTM]>;
38 "xtest", [(set EFLAGS, (X86xtest))]>, TB, Requires<[HasTSX]>;
H A DX86InstrInfo.td1435 OpSize16, TB;
1439 OpSize32, TB;
1468 >, TB;
1508 OpSize16, TB;
1511 OpSize32, TB;
1519 OpSize16, TB;
1522 OpSize32, TB;
1552 OpSize16, TB;
1599 OpSize32, TB;
1607 OpSize16, TB;
[all …]
H A DX86InstrShiftRotate.td696 TB, OpSize16;
702 TB, OpSize16;
718 TB;
724 TB;
748 TB, OpSize32;
755 TB, OpSize32;
762 TB;
769 TB;
809 TB, OpSize16;
839 TB;
[all …]
H A DX86Instr3DNow.td16 : I<o, F, outs, ins, asm, pat>, TB, Requires<[Has3DNow]> {
95 [(prefetch addr:$addr, (i32 1), (i32 3), (i32 1))]>, TB,
H A DX86InstrFormats.td125 def TB : Map<1>;
168 class TB { Map OpMap = TB; }
175 class PS : TB { Prefix OpPrefix = PS; }
176 class PD : TB { Prefix OpPrefix = PD; }
177 class XD : TB { Prefix OpPrefix = XD; }
178 class XS : TB { Prefix OpPrefix = XS; }
879 // MMXI - MMX instructions with TB prefix.
880 // MMXI32 - MMX instructions with TB prefix valid only in 32 bit mode.
881 // MMXI64 - MMX instructions with TB prefix valid only in 64 bit mode.
H A DX86InstrControl.td77 [], IIC_Jcc>, OpSize16, TB;
79 [], IIC_Jcc>, TB, OpSize32;
/minix/external/bsd/llvm/dist/clang/test/CXX/special/class.dtor/
H A Dp3-0x.cpp66 struct TB { struct
67 ~TB() throw(int);
72 TB<T> b;
114 TB<T> b;
/minix/external/bsd/kyua-cli/dist/utils/
H A Dunits_test.cpp42 using units::TB; in ATF_TEST_CASE_BODY()
45 ATF_REQUIRE_EQ("2.00T", units::bytes(2 * TB).format()); in ATF_TEST_CASE_BODY()
46 ATF_REQUIRE_EQ("45.12T", units::bytes(45 * TB + 120 * GB).format()); in ATF_TEST_CASE_BODY()
94 using units::TB; in ATF_TEST_CASE_BODY()
98 ATF_REQUIRE_EQ(units::bytes(TB), units::bytes::parse("1T")); in ATF_TEST_CASE_BODY()
99 ATF_REQUIRE_EQ(units::bytes(TB), units::bytes::parse("1t")); in ATF_TEST_CASE_BODY()
H A Dunits.cpp78 case 'T': case 't': multiplier = TB; break; in parse()
115 if (_count >= TB) { in format()
116 return F("%.2sT") % (static_cast< float >(_count) / TB); in format()
H A Dmemory_test.cpp53 ATF_REQUIRE(memory < 100 * units::TB); // Large enough for now... in ATF_TEST_CASE_BODY()
H A Dunits.hpp59 const uint64_t TB = int64_t(1) << 40; variable
/minix/external/bsd/llvm/dist/llvm/test/CodeGen/X86/
H A Disel-sink2.ll10 br i1 %T, label %TB, label %F
11 TB:
/minix/external/bsd/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonHardwareLoops.cpp376 MachineBasicBlock *TB = nullptr, *FB = nullptr; in findInductionRegister() local
484 MachineBasicBlock *TB = nullptr, *FB = nullptr; in getLoopTripCount() local
493 assert (TB && "Latch block without a branch?"); in getLoopTripCount()
495 if (!TB || (FB && TB != Header && FB != Header)) in getLoopTripCount()
502 bool Negated = (Cond.size() > 1) ^ (TB != Header); in getLoopTripCount()
1298 MachineBasicBlock *TB = nullptr, *FB = nullptr; in fixupInductionVariable() local
1309 if (TB != Header && FB != Header) in fixupInductionVariable()
1436 MachineBasicBlock *TB = nullptr, *FB = nullptr; in createPreheaderForLoop() local
1522 TB = FB = nullptr; in createPreheaderForLoop()
1539 TB = FB = nullptr; in createPreheaderForLoop()
[all …]
/minix/external/bsd/llvm/dist/clang/test/SemaCXX/
H A Dvirtual-override.cpp225 template <int N> struct TB {}; struct
226 struct D : public TB<0> {};
230 virtual TB<N>* f2(); // expected-note{{overridden virtual function is here}}
/minix/external/bsd/libarchive/dist/libarchive/test/
H A Dtest_tar_large.c74 #define TB ((int64_t)1024 * GB) macro
215 256 * GB, 1 * TB, 0 }; in DEFINE_TEST()
/minix/external/bsd/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64SchedA57.td504 def : InstRW<[A57Write_3cyc_1V], (instregex "^TB[LX]v8i8One")>;
505 def : InstRW<[A57Write_6cyc_2V], (instregex "^TB[LX]v8i8Two")>;
506 def : InstRW<[A57Write_9cyc_3V], (instregex "^TB[LX]v8i8Three")>;
507 def : InstRW<[A57Write_12cyc_4V], (instregex "^TB[LX]v8i8Four")>;
509 def : InstRW<[A57Write_6cyc_3V], (instregex "^TB[LX]v16i8One")>;
510 def : InstRW<[A57Write_9cyc_5V], (instregex "^TB[LX]v16i8Two")>;
511 def : InstRW<[A57Write_12cyc_7V], (instregex "^TB[LX]v16i8Three")>;
512 def : InstRW<[A57Write_15cyc_9V], (instregex "^TB[LX]v16i8Four")>;
/minix/external/bsd/llvm/dist/llvm/utils/TableGen/
H A DX86RecognizableInstr.cpp108 OB = 0, TB = 1, T8 = 2, TA = 3, XOP8 = 4, XOP9 = 5, XOPA = 6 enumerator
818 case X86Local::TB: in emitDecodePath()
827 case X86Local::TB: opcodeType = TWOBYTE; break; in emitDecodePath()
/minix/distrib/sets/lists/text/
H A Dmi117 ./usr/share/groff_font/devX100-12/TB text-groff-font share,groff
135 ./usr/share/groff_font/devX100/TB text-groff-font share,groff
153 ./usr/share/groff_font/devX75-12/TB text-groff-font share,groff
171 ./usr/share/groff_font/devX75/TB text-groff-font share,groff
223 ./usr/share/groff_font/devdvi/TB text-groff-font share,groff
276 ./usr/share/groff_font/devhtml/TB text-obsolete obsolete
311 ./usr/share/groff_font/devlbp/TB text-groff-font share,groff
346 ./usr/share/groff_font/devlj4/TB text-groff-font share,groff
404 ./usr/share/groff_font/devps/TB text-groff-font share,groff
/minix/external/bsd/llvm/dist/llvm/lib/Target/X86/MCTargetDesc/
H A DX86BaseInfo.h375 TB = 1 << OpMapShift, enumerator

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