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Searched refs:VCGT (Results 1 – 8 of 8) sorted by relevance

/minix/external/bsd/llvm/dist/llvm/test/CodeGen/ARM/
H A Dvfcmp.ll17 ; olt is implemented with VCGT
39 ; uge is implemented with VCGT/VMVN
51 ; ule is implemented with VCGT/VMVN
87 ; ueq is implemented with VCGT/VCGT/VORR/VMVN
101 ; one is implemented with VCGT/VCGT/VORR
114 ; uno is implemented with VCGT/VCGE/VORR/VMVN
128 ; ord is implemented with VCGT/VCGE/VORR
H A Dvicmp.ll6 ; to VCGT and VCGE. Test all the operand types for not-equal but only sample
/minix/external/bsd/llvm/dist/llvm/lib/Target/ARM/
H A DARMISelLowering.h106 VCGT, // Vector compare greater than. enumerator
H A DARMISelLowering.cpp1072 case ARMISD::VCGT: return "ARMISD::VCGT"; in getTargetNodeName()
4510 case ISD::SETGT: Opc = ARMISD::VCGT; break; in LowerVSETCC()
4516 case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break; in LowerVSETCC()
4525 Op0 = DAG.getNode(ARMISD::VCGT, dl, CmpVT, TmpOp1, TmpOp0); in LowerVSETCC()
4526 Op1 = DAG.getNode(ARMISD::VCGT, dl, CmpVT, TmpOp0, TmpOp1); in LowerVSETCC()
4534 Op0 = DAG.getNode(ARMISD::VCGT, dl, CmpVT, TmpOp1, TmpOp0); in LowerVSETCC()
4545 case ISD::SETGT: Opc = ARMISD::VCGT; break; in LowerVSETCC()
4587 else if (Opc == ARMISD::VCGT) in LowerVSETCC()
4601 case ARMISD::VCGT: in LowerVSETCC()
H A DARMScheduleSwift.td1585 "VACLE", "VACLT", "VCEQ", "VCGE", "VCGT", "VCLE", "VCLT", "VRSHL",
H A DARMScheduleA9.td2411 // VSBH/VRSBH/VHSUB/VQSUB/VABD/VCEQ/VCGE/VCGT/VMAX/VMIN/VPMAX/VPMIN/VABDL
H A DARMInstrNEON.td501 def NEONvcgt : SDNode<"ARMISD::VCGT", SDTARMVCMP>;
4514 // VCGT : Vector Compare Greater Than
7507 // VCLT (register) is an assembler alias for VCGT w/ the operands reversed.
7539 // VCLT (register) is an assembler alias for VCGT w/ the operands reversed.
/minix/external/bsd/llvm/dist/clang/include/clang/Basic/
H A Darm_neon.td539 def VCGT : SOpInst<"vcgt", "udd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_GT>;