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/minix/external/bsd/llvm/dist/llvm/test/MC/AArch64/
H A Dneon-scalar-shift-imm.s124 sqshrn b10, h15, #5
146 sqrshrn b10, h13, #2
157 uqrshrn b10, h12, #5
/minix/external/bsd/llvm/dist/llvm/lib/Target/Sparc/
H A DSparcInstrVIS.td186 def FHADDS : F3_3<0b10, 0b110100, 0b001100001,
189 def FHADDD : F3_3<0b10, 0b110100, 0b001100010,
192 def FHSUBS : F3_3<0b10, 0b110100, 0b001100101,
195 def FHSUBD : F3_3<0b10, 0b110100, 0b001100110,
207 def FNADDS : F3_3<0b10, 0b110100, 0b001010001,
210 def FNADDD : F3_3<0b10, 0b110100, 0b001010010,
213 def FNHADDS : F3_3<0b10, 0b110100, 0b001110001,
216 def FNHADDD : F3_3<0b10, 0b110100, 0b001110010,
220 def FNMULS : F3_3<0b10, 0b110100, 0b001011001,
223 def FNMULD : F3_3<0b10, 0b110100, 0b001011010,
[all …]
H A DSparcInstr64Bit.td310 let Uses = [ICC], cc = 0b10 in
315 let intcc = 1, cc = 0b10 in {
328 let intcc = 1, opf_cc = 0b10 in {
545 let Predicates = [Is64Bit], hasSideEffects = 1, Uses = [ICC], cc = 0b10 in
/minix/tests/ipf/expected/
H A Dni13 …202 0202 0b00 5773 0000 0000 4500 0028 0000 4000 0111 6dba 0202 0202 0404 0404 afc9 829e 0014 6b10
5 …000 0000 4500 0028 0000 4000 0111 6dba 0202 0202 0404 0404 afc9 829e 0014 6b10 0402 0000 3be5 468d…
/minix/external/bsd/llvm/dist/llvm/lib/Target/Mips/
H A DMipsMSAInstrInfo.td453 class ADDV_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b001110>;
497 class BCLR_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b001101>;
545 class BNZ_W_ENC : MSA_CBRANCH_FMT<0b111, 0b10>;
552 class BSELI_B_ENC : MSA_I8_FMT<0b10, 0b000001>;
566 class BZ_W_ENC : MSA_CBRANCH_FMT<0b110, 0b10>;
573 class CEQ_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b001111>;
875 class LD_W_ENC : MSA_MI10_FMT<0b10, 0b1000>;
993 class NORI_B_ENC : MSA_I8_FMT<0b10, 0b000000>;
1026 class SHF_W_ENC : MSA_I8_FMT<0b10, 0b000010>;
1040 class SLL_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b001101>;
[all …]
/minix/external/bsd/llvm/dist/llvm/test/MC/Disassembler/SystemZ/
H A Dtrunc-02.txt2 # If the top bits are 0b10, the instruction must be 4 bytes long.
/minix/tests/ipf/input/
H A Dni75 afc9 829e 0014 6b10 0402 0000
H A Dni16 afc9 829e 0014 6b10
/minix/external/bsd/llvm/dist/llvm/lib/Target/ARM/
H A DARMInstrNEON.td929 : NLdSt<0, 0b10, op11_8, op7_4,
969 : NLdSt<0, 0b10, op11_8, op7_4,
988 : NLdSt<0, 0b10, op11_8, op7_4,
1247 : NLdStLn<1, 0b10, op11_8, op7_4,
1284 : NLdStLn<1, 0b10, op11_8, op7_4,
1324 : NLdStLn<1, 0b10, op11_8, op7_4,
1411 def _fixed : NLdSt<1, 0b10, 0b1100, op7_4,
1430 def _fixed : NLdSt<1, 0b10, 0b1100, op7_4,
1487 def _fixed : NLdSt<1, 0b10, 0b1101, op7_4,
1567 : NLdSt<1, 0b10, 0b1111, op7_4,
[all …]
H A DARMInstrVFP.td334 def VMULD : ADbI<0b11100, 0b10, 0, 0,
340 def VMULS : ASbIn<0b11100, 0b10, 0, 0,
349 def VNMULD : ADbI<0b11100, 0b10, 1, 0,
354 def VNMULS : ASbI<0b11100, 0b10, 1, 0,
382 defm VSELGE : vsel_inst<"ge", 0b10, 10>;
683 defm VCVTP : vcvt_inst<"p", 0b10, fceil>;
759 defm VRINTP : vrint_inst_anpm<"p", 0b10, fceil>;
1374 def VFMAD : ADbI<0b11101, 0b10, 0, 0,
1382 def VFMAS : ASbIn<0b11101, 0b10, 0, 0,
1409 def VFMSD : ADbI<0b11101, 0b10, 1, 0,
[all …]
H A DARMInstrThumb2.td785 let Inst{25-24} = 0b10;
1225 let Inst{25-24} = 0b10;
2433 let Inst{28-27} = 0b10;
2711 let Inst{5-4} = 0b10;
2791 let Inst{5-4} = 0b10;
2950 let Inst{7-6} = 0b10;
3062 let Inst{7-6} = 0b10;
3437 let Inst{15-14} = 0b10;
3518 let Inst{15-14} = 0b10;
3583 let Inst{15-14} = 0b10;
[all …]
/minix/external/bsd/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfo.td455 let Inst{25-24} = !if(isHi, 0b10, 0b01);
977 let Inst{22-21} = !if(isMax, 0b10, 0b01);
1171 def C2_not : T_LOGICAL_1OP<"not", 0b10>;
2483 def M2_mpyd_hl_s0: T_M2_mpyd<0b10, 0, 0, 0>;
2488 def M2_mpyd_hl_s1: T_M2_mpyd<0b10, 0, 1, 0>;
3276 def A2_absp : T_S2op_3 <"abs", 0b10, 0b110>;
3277 def A2_negp : T_S2op_3 <"neg", 0b10, 0b101>;
3278 def A2_notp : T_S2op_3 <"not", 0b10, 0b100>;
3756 defm J2_ploop2s : SPLOOP_ri<"2", 0b10>;
3790 let Inst{27-26} = 0b10;
[all …]
H A DHexagonInstrInfoV4.td134 def C4_cmplte : T_ALU32_3op_cmp<"!cmp.gt", 0b10, 1, 0>;
1016 defm S4_storeiri : ST_Imm<"memw", "STriw", u6_2Imm, 0b10>;
1217 u6_2Ext, 0b10>, AddrModeRel;
1631 def C4_or_and : T_LOGICAL_3OP<"or", "and", 0b10, 0>;
1635 def C4_or_andn : T_LOGICAL_3OP<"or", "and", 0b10, 1>;
1882 def S4_or_ori : T_CompOR <"or", 0b10, or>;
1998 def C4_nbitsclr : T_TEST_BITS_REG<"!bitsclr", 0b10, 1>;
1999 def C4_nbitsclri : T_TEST_BITS_IMM<"!bitsclr", 0b10, 1>;
2462 defm memopw_io : MemOp_base <"memw", 0b10, u6_2Ext>;
3430 ST_Abs_NV <"memw", "STriw", u16_2Imm, 0b10>;
[all …]
H A DHexagonInstrInfoV3.td128 let Inst{22-21} = !if(isMax, 0b10, 0b01);
/minix/external/bsd/llvm/dist/llvm/test/TableGen/
H A Dmath.td5 bits<2> b = 0b10;
/minix/external/bsd/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.td399 defm MOVZ : MoveImmediate<0b10, "movz">;
646 defm ASRV : Shift<0b10, "asr", sra>;
748 defm EON : LogicalReg<0b10, 1, "eon",
750 defm EOR : LogicalReg<0b10, 0, "eor", xor>;
846 defm UBFM : BitfieldImm<0b10, "ubfm">;
1187 defm LDRSW : Load32RO<0b10, 0, 0b10, GPR64, "ldrsw", i64, sextloadi32>;
1493 defm LDRSW : LoadUI<0b10, 0, 0b10, GPR64, uimm12s4, "ldrsw",
1704 : LoadUnscaled<0b10, 0, 0b10, GPR64, "ldursw",
1746 defm LDTRSW : LoadUnprivileged<0b10, 0, 0b10, GPR64, "ldtrsw">;
1771 def LDRSWpre : LoadPreIdx<0b10, 0, 0b10, GPR64, "ldrsw">;
[all …]
H A DAArch64InstrFormats.td2081 let Inst{11-10} = 0b10;
2461 let Inst{11-10} = 0b10;
2539 let Inst{11-10} = 0b10;
2611 let Inst{11-10} = 0b10;
2683 let Inst{11-10} = 0b10;
2755 let Inst{11-10} = 0b10;
2829 let Inst{11-10} = 0b10;
2938 let Inst{11-10} = 0b10;
3787 let Inst{11-10} = 0b10;
4317 let Inst{11-10} = 0b10;
[all …]
/minix/external/bsd/llvm/dist/clang/test/CodeGenCXX/
H A Dmangle-ms-return-qualifiers.cpp48 const volatile float &b10() { return *(float*)0; } in b10() function
/minix/external/bsd/llvm/dist/clang/test/SemaCXX/
H A Dconstant-expression.cpp44 b10 : sizeof(Struct),
H A Duninitialized.cpp424 …B b10 = getB(-b10.x); // expected-warning {{variable 'b10' is uninitialized when used within its … in setupB() local
459 B b10 = getB(-b10.x); // expected-warning {{variable 'b10' is uninitialized when used within its o… variable
1123 B b10 = { {b10.a1.i2} }; // expected-warning{{uninitialized}} variable
1181 B b10 = { {b10.a1.i2} }; // expected-warning{{uninitialized}} member
1210 b10{ {b10.a1.i2} }, // expected-warning{{uninitialized}}
/minix/external/bsd/file/dist/magic/magdir/
H A Dfsav27 #>>>>10 byte 9 \b10-
/minix/external/bsd/llvm/dist/llvm/test/MC/Disassembler/AArch64/
H A Dbasic-a64-undefined.txt27 # Only unallocated (int-register) variants are: opc=0b11, size=0b10, 0b11
/minix/external/bsd/llvm/dist/llvm/test/MC/Disassembler/ARM/
H A Dinvalid-armv7.txt437 # VST1 multi-element, type == 0b0111, align == 0b10 -> undefined
452 # VST1 multi-element, type == 0b0110, align == 0b10 -> undefined
477 # VST3 multi-element, align = 0b10 -> undefined
/minix/external/bsd/llvm/dist/llvm/test/CodeGen/Mips/
H A Dra-allocatable.ll24 @b10 = external global i32*
132 %21 = load i32** @b10, align 4
/minix/external/bsd/bind/dist/bin/tests/system/rpz/
H A Dtests.sh414 soa=`$DIG -p 5300 +short soa bl.tld2 @10.53.0.3 -b10.53.0.3`
425 soa=`$DIG -p 5300 +short soa bl.tld2 @10.53.0.3 -b10.53.0.3`

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