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Searched refs:getSchedClass (Results 1 – 21 of 21) sorted by relevance

/minix/external/bsd/llvm/dist/llvm/lib/CodeGen/
H A DTargetSchedule.cpp79 int UOps = InstrItins.getNumMicroOps(MI->getDesc().getSchedClass()); in getNumMicroOps()
105 unsigned SchedClass = MI->getDesc().getSchedClass(); in resolveSchedClass()
168 unsigned DefClass = DefMI->getDesc().getSchedClass(); in computeOperandLatency()
230 unsigned SCIdx = TII->get(Opcode).getSchedClass(); in computeInstrLatency()
H A DTargetInstrInfo.cpp737 unsigned DefClass = get(DefNode->getMachineOpcode()).getSchedClass(); in getOperandLatency()
740 unsigned UseClass = get(UseNode->getMachineOpcode()).getSchedClass(); in getOperandLatency()
752 return ItinData->getStageLatency(get(N->getMachineOpcode()).getSchedClass()); in getInstrLatency()
765 unsigned Class = MI->getDesc().getSchedClass(); in getNumMicroOps()
800 return ItinData->getStageLatency(MI->getDesc().getSchedClass()); in getInstrLatency()
809 unsigned DefClass = DefMI->getDesc().getSchedClass(); in hasLowDefLatency()
820 unsigned DefClass = DefMI->getDesc().getSchedClass(); in getOperandLatency()
821 unsigned UseClass = UseMI->getDesc().getSchedClass(); in getOperandLatency()
868 unsigned DefClass = DefMI->getDesc().getSchedClass(); in computeOperandLatency()
H A DScoreboardHazardRecognizer.cpp134 unsigned idx = MCID->getSchedClass(); in getHazardType()
194 unsigned idx = MCID->getSchedClass(); in EmitInstruction()
H A DDFAPacketizer.cpp67 unsigned InsnClass = MID->getSchedClass(); in canReserveResources()
79 unsigned InsnClass = MID->getSchedClass(); in reserveResources()
H A DMachineCombiner.cpp262 unsigned Idx = TII->get(Opc).getSchedClass(); in instr2instrSC()
H A DMachineScheduler.cpp1614 const MCSchedClassDesc *SC = DAG->getSchedClass(&*I); in init()
1695 const MCSchedClassDesc *SC = DAG->getSchedClass(SU); in checkHazard()
1898 const MCSchedClassDesc *SC = DAG->getSchedClass(SU); in bumpNode()
2123 const MCSchedClassDesc *SC = DAG->getSchedClass(SU); in initResourceDelta()
H A DScheduleDAGInstrs.cpp721 const MCSchedClassDesc *SC = getSchedClass(SU); in initSUnits()
/minix/external/bsd/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64StorePairSuppress.cpp82 unsigned SCIdx = TII->get(AArch64::STPDi).getSchedClass(); in shouldAddSTPToBlock()
/minix/external/bsd/llvm/dist/llvm/lib/MC/MCDisassembler/
H A DDisassembler.cpp170 unsigned SCClass = Desc.getSchedClass(); in getItineraryLatency()
197 unsigned SCClass = Desc.getSchedClass(); in getLatency()
/minix/external/bsd/llvm/dist/llvm/utils/TableGen/
H A DCodeGenSchedule.h340 CodeGenSchedClass &getSchedClass(unsigned Idx) { in getSchedClass() function
344 const CodeGenSchedClass &getSchedClass(unsigned Idx) const { in getSchedClass() function
H A DSubtargetEmitter.cpp601 ", // " << j << " " << SchedModels.getSchedClass(j).Name << "\n"; in EmitItineraries()
1155 assert(SchedModels.getSchedClass(0).Name == "NoInstrModel" in EmitSchedClassTables()
1163 const CodeGenSchedClass &SchedClass = SchedModels.getSchedClass(SCIdx); in EmitSchedClassTables()
1325 const CodeGenSchedClass &SC = SchedModels.getSchedClass(*VCI); in EmitSchedModelHelpers()
1360 << SchedModels.getSchedClass(TI->ToClassIdx).Name << '\n'; in EmitSchedModelHelpers()
H A DCodeGenSchedule.cpp542 CodeGenSchedClass &SC = getSchedClass(SCIdx); in collectSchedClasses()
1321 SchedModels.getSchedClass(FromClassIdx).Transitions.push_back(SCTrans); in inferFromTransitions()
/minix/external/bsd/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCHazardRecognizers.cpp68 if (!PredMCID || PredMCID->getSchedClass() != PPC::Sched::IIC_SprMTSPR) in isBCTRAfterSet()
92 unsigned IIC = MCID->getSchedClass(); in mustComeFirst()
/minix/external/bsd/llvm/dist/llvm/include/llvm/CodeGen/
H A DScheduleDAGInstrs.h172 const MCSchedClassDesc *getSchedClass(SUnit *SU) const { in getSchedClass() function
/minix/external/bsd/llvm/dist/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCInst.cpp75 II->beginStage(QII->get(this->getOpcode()).getSchedClass()); in getUnits()
/minix/external/bsd/llvm/dist/llvm/include/llvm/MC/
H A DMCInstrDesc.h621 unsigned getSchedClass() const { in getSchedClass() function
/minix/external/bsd/llvm/dist/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.cpp2727 int UOps = ItinData->getNumMicroOps(Desc.getSchedClass()); in getNumMicroOpsSwiftLdSt()
2983 unsigned Class = Desc.getSchedClass(); in getNumMicroOps()
3271 unsigned DefClass = DefMCID.getSchedClass(); in getOperandLatency()
3272 unsigned UseClass = UseMCID.getSchedClass(); in getOperandLatency()
3719 int Latency = ItinData->getOperandCycle(DefMCID.getSchedClass(), DefIdx); in getOperandLatency()
3969 unsigned Class = MCID.getSchedClass(); in getInstrLatency()
3999 return ItinData->getStageLatency(get(Opcode).getSchedClass()); in getInstrLatency()
4036 unsigned DefClass = DefMI->getDesc().getSchedClass(); in hasLowDefLatency()
H A DARMISelLowering.cpp1203 Itins->getOperandCycle(MCID.getSchedClass(), 0) > 2) in getSchedulingPreference()
/minix/external/bsd/llvm/dist/llvm/lib/Target/R600/
H A DR600InstrInfo.cpp184 return (get(Opcode).getSchedClass() == AMDGPU::Sched::TransALU); in isTransOnly()
192 return (get(Opcode).getSchedClass() == AMDGPU::Sched::VecALU); in isVectorOnly()
/minix/external/bsd/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonVLIWPacketizer.cpp965 unsigned SchedClass = TID.getSchedClass(); in ignorePseudoInstruction()
/minix/external/bsd/llvm/dist/llvm/docs/
H A DWritingAnLLVMBackend.rst1012 Instruction itineraries can be queried using MCDesc::getSchedClass(). The