/minix/external/bsd/llvm/dist/llvm/lib/CodeGen/ |
H A D | TargetSchedule.cpp | 79 int UOps = InstrItins.getNumMicroOps(MI->getDesc().getSchedClass()); in getNumMicroOps() 105 unsigned SchedClass = MI->getDesc().getSchedClass(); in resolveSchedClass() 168 unsigned DefClass = DefMI->getDesc().getSchedClass(); in computeOperandLatency() 230 unsigned SCIdx = TII->get(Opcode).getSchedClass(); in computeInstrLatency()
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H A D | TargetInstrInfo.cpp | 737 unsigned DefClass = get(DefNode->getMachineOpcode()).getSchedClass(); in getOperandLatency() 740 unsigned UseClass = get(UseNode->getMachineOpcode()).getSchedClass(); in getOperandLatency() 752 return ItinData->getStageLatency(get(N->getMachineOpcode()).getSchedClass()); in getInstrLatency() 765 unsigned Class = MI->getDesc().getSchedClass(); in getNumMicroOps() 800 return ItinData->getStageLatency(MI->getDesc().getSchedClass()); in getInstrLatency() 809 unsigned DefClass = DefMI->getDesc().getSchedClass(); in hasLowDefLatency() 820 unsigned DefClass = DefMI->getDesc().getSchedClass(); in getOperandLatency() 821 unsigned UseClass = UseMI->getDesc().getSchedClass(); in getOperandLatency() 868 unsigned DefClass = DefMI->getDesc().getSchedClass(); in computeOperandLatency()
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H A D | ScoreboardHazardRecognizer.cpp | 134 unsigned idx = MCID->getSchedClass(); in getHazardType() 194 unsigned idx = MCID->getSchedClass(); in EmitInstruction()
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H A D | DFAPacketizer.cpp | 67 unsigned InsnClass = MID->getSchedClass(); in canReserveResources() 79 unsigned InsnClass = MID->getSchedClass(); in reserveResources()
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H A D | MachineCombiner.cpp | 262 unsigned Idx = TII->get(Opc).getSchedClass(); in instr2instrSC()
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H A D | MachineScheduler.cpp | 1614 const MCSchedClassDesc *SC = DAG->getSchedClass(&*I); in init() 1695 const MCSchedClassDesc *SC = DAG->getSchedClass(SU); in checkHazard() 1898 const MCSchedClassDesc *SC = DAG->getSchedClass(SU); in bumpNode() 2123 const MCSchedClassDesc *SC = DAG->getSchedClass(SU); in initResourceDelta()
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H A D | ScheduleDAGInstrs.cpp | 721 const MCSchedClassDesc *SC = getSchedClass(SU); in initSUnits()
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/minix/external/bsd/llvm/dist/llvm/lib/Target/AArch64/ |
H A D | AArch64StorePairSuppress.cpp | 82 unsigned SCIdx = TII->get(AArch64::STPDi).getSchedClass(); in shouldAddSTPToBlock()
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/minix/external/bsd/llvm/dist/llvm/lib/MC/MCDisassembler/ |
H A D | Disassembler.cpp | 170 unsigned SCClass = Desc.getSchedClass(); in getItineraryLatency() 197 unsigned SCClass = Desc.getSchedClass(); in getLatency()
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/minix/external/bsd/llvm/dist/llvm/utils/TableGen/ |
H A D | CodeGenSchedule.h | 340 CodeGenSchedClass &getSchedClass(unsigned Idx) { in getSchedClass() function 344 const CodeGenSchedClass &getSchedClass(unsigned Idx) const { in getSchedClass() function
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H A D | SubtargetEmitter.cpp | 601 ", // " << j << " " << SchedModels.getSchedClass(j).Name << "\n"; in EmitItineraries() 1155 assert(SchedModels.getSchedClass(0).Name == "NoInstrModel" in EmitSchedClassTables() 1163 const CodeGenSchedClass &SchedClass = SchedModels.getSchedClass(SCIdx); in EmitSchedClassTables() 1325 const CodeGenSchedClass &SC = SchedModels.getSchedClass(*VCI); in EmitSchedModelHelpers() 1360 << SchedModels.getSchedClass(TI->ToClassIdx).Name << '\n'; in EmitSchedModelHelpers()
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H A D | CodeGenSchedule.cpp | 542 CodeGenSchedClass &SC = getSchedClass(SCIdx); in collectSchedClasses() 1321 SchedModels.getSchedClass(FromClassIdx).Transitions.push_back(SCTrans); in inferFromTransitions()
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/minix/external/bsd/llvm/dist/llvm/lib/Target/PowerPC/ |
H A D | PPCHazardRecognizers.cpp | 68 if (!PredMCID || PredMCID->getSchedClass() != PPC::Sched::IIC_SprMTSPR) in isBCTRAfterSet() 92 unsigned IIC = MCID->getSchedClass(); in mustComeFirst()
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/minix/external/bsd/llvm/dist/llvm/include/llvm/CodeGen/ |
H A D | ScheduleDAGInstrs.h | 172 const MCSchedClassDesc *getSchedClass(SUnit *SU) const { in getSchedClass() function
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/minix/external/bsd/llvm/dist/llvm/lib/Target/Hexagon/MCTargetDesc/ |
H A D | HexagonMCInst.cpp | 75 II->beginStage(QII->get(this->getOpcode()).getSchedClass()); in getUnits()
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/minix/external/bsd/llvm/dist/llvm/include/llvm/MC/ |
H A D | MCInstrDesc.h | 621 unsigned getSchedClass() const { in getSchedClass() function
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/minix/external/bsd/llvm/dist/llvm/lib/Target/ARM/ |
H A D | ARMBaseInstrInfo.cpp | 2727 int UOps = ItinData->getNumMicroOps(Desc.getSchedClass()); in getNumMicroOpsSwiftLdSt() 2983 unsigned Class = Desc.getSchedClass(); in getNumMicroOps() 3271 unsigned DefClass = DefMCID.getSchedClass(); in getOperandLatency() 3272 unsigned UseClass = UseMCID.getSchedClass(); in getOperandLatency() 3719 int Latency = ItinData->getOperandCycle(DefMCID.getSchedClass(), DefIdx); in getOperandLatency() 3969 unsigned Class = MCID.getSchedClass(); in getInstrLatency() 3999 return ItinData->getStageLatency(get(Opcode).getSchedClass()); in getInstrLatency() 4036 unsigned DefClass = DefMI->getDesc().getSchedClass(); in hasLowDefLatency()
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H A D | ARMISelLowering.cpp | 1203 Itins->getOperandCycle(MCID.getSchedClass(), 0) > 2) in getSchedulingPreference()
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/minix/external/bsd/llvm/dist/llvm/lib/Target/R600/ |
H A D | R600InstrInfo.cpp | 184 return (get(Opcode).getSchedClass() == AMDGPU::Sched::TransALU); in isTransOnly() 192 return (get(Opcode).getSchedClass() == AMDGPU::Sched::VecALU); in isVectorOnly()
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/minix/external/bsd/llvm/dist/llvm/lib/Target/Hexagon/ |
H A D | HexagonVLIWPacketizer.cpp | 965 unsigned SchedClass = TID.getSchedClass(); in ignorePseudoInstruction()
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/minix/external/bsd/llvm/dist/llvm/docs/ |
H A D | WritingAnLLVMBackend.rst | 1012 Instruction itineraries can be queried using MCDesc::getSchedClass(). The
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