/minix/external/bsd/llvm/dist/llvm/test/CodeGen/SystemZ/ |
H A D | spill-01.ll | 52 %val5 = load i32 *%ptr5 62 store i32 %val5, i32 *%ptr5 90 %val5 = load i32 *%ptr5 102 store i32 %val5, i32 *%ptr5 132 %val5 = load i64 *%ptr5 178 %val5 = load float *%ptr5 222 %val5 = load double *%ptr5 332 %val5 = load i32 *@g5 345 store i32 %val5, i32 *@g5 364 %val5 = load i64 *@h5 [all …]
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H A D | int-add-11.ll | 142 %val5 = load volatile i32 *%ptr 163 %add5 = add i32 %val5, 127 182 %new5 = phi i32 [ %val5, %entry ], [ %add5, %add ] 225 %val5 = load volatile i32 *%ptr 246 %add5 = add i32 %val5, -128 265 %new5 = phi i32 [ %val5, %entry ], [ %add5, %add ]
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H A D | int-add-12.ll | 141 %val5 = load volatile i64 *%ptr 162 %add5 = add i64 %val5, 127 181 %new5 = phi i64 [ %val5, %entry ], [ %add5, %add ] 224 %val5 = load volatile i64 *%ptr 245 %add5 = add i64 %val5, -128 264 %new5 = phi i64 [ %val5, %entry ], [ %add5, %add ]
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H A D | fp-conv-02.ll | 84 %val5 = load volatile float *%ptr2 102 %ext5 = fpext float %val5 to double 120 store volatile float %val5, float *%ptr2
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H A D | fp-conv-03.ll | 102 %val5 = load volatile float *%ptr2 120 %ext5 = fpext float %val5 to fp128 138 store volatile float %val5, float *%ptr2
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H A D | fp-conv-04.ll | 102 %val5 = load volatile double *%ptr2 120 %ext5 = fpext double %val5 to fp128 138 store volatile double %val5, double *%ptr2
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H A D | fp-mul-01.ll | 97 %val5 = load float *%ptr5 111 %mul5 = fmul float %mul4, %val5
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H A D | fp-sub-01.ll | 97 %val5 = load float *%ptr5 111 %sub5 = fsub float %sub4, %val5
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H A D | fp-sub-02.ll | 97 %val5 = load double *%ptr5 111 %sub5 = fsub double %sub4, %val5
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H A D | fp-add-01.ll | 97 %val5 = load float *%ptr5 111 %add5 = fadd float %add4, %val5
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H A D | fp-add-02.ll | 97 %val5 = load double *%ptr5 111 %add5 = fadd double %add4, %val5
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H A D | fp-div-01.ll | 97 %val5 = load float *%ptr5 111 %div5 = fdiv float %div4, %val5
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H A D | fp-div-02.ll | 97 %val5 = load double *%ptr5 111 %div5 = fdiv double %div4, %val5
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/minix/external/bsd/llvm/dist/llvm/test/CodeGen/AArch64/ |
H A D | floatdp_2source.ll | 19 %val5 = fsub float %val4, %val2 22 store volatile float %val5, float* @varfloat 47 %val5 = fsub double %val4, %val2 50 store volatile double %val5, double* @vardouble
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H A D | arm64-extract.ll | 8 %val5 = or i64 %left, %right 10 ret i64 %val5 17 %val5 = or i32 %left, %right 19 ret i32 %val5
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H A D | extract.ll | 7 %val5 = or i64 %left, %right 9 ret i64 %val5 16 %val5 = or i32 %left, %right 18 ret i32 %val5
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H A D | regress-w29-reserved-with-fp.ll | 14 %val5 = load volatile i32* @var 29 store volatile i32 %val5, i32* @var
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H A D | addsub-shifted.ll | 42 %val5 = add i64 %lhs64, %shift5 43 store volatile i64 %val5, i64* @var64 105 %val5 = add i64 %lhs64, %shift5 106 store volatile i64 %val5, i64* @var64 164 %val5 = add i64 %lhs64, %shift5 165 store volatile i64 %val5, i64* @var64 276 %val5 = sub i64 0, %shift5 277 %tst5 = icmp ne i64 %lhs64, %val5
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H A D | callee-save.ll | 19 %val5 = load volatile float* @var 52 store volatile float %val5, float* @var
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/minix/external/bsd/llvm/dist/llvm/test/CodeGen/ARM/ |
H A D | gpr-paired-spill-thumbinst.ll | 13 %val5 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr) 26 store volatile i64 %val5, i64* %addr
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H A D | inlineasm-64bit.ll | 13 define void @multi_writes(i64* %p, i64 %val1, i64 %val2, i64 %val3, i64 %val4, i64 %val5, i64 %val6… 37 …"r,r,r,r,r,r,r"(i64* %p, i64 %val1, i64 %val2, i64 %val3, i64 %val4, i64 %val5, i64 %val6) nounwind 39 …r,r,r"(i64* %incdec.ptr, i64 %val1, i64 %val2, i64 %val3, i64 %val4, i64 %val5, i64 %val6) nounwind 40 …r,r,r"(i64* %incdec.ptr, i64 %val1, i64 %val2, i64 %val3, i64 %val4, i64 %val5, i64 %val6) nounwind
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H A D | gpr-paired-spill.ll | 10 %val5 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr) 40 store volatile i64 %val5, i64* %addr
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/minix/external/bsd/llvm/dist/llvm/test/CodeGen/R600/ |
H A D | ds_read2_offset_order.ll | 37 %val5 = load float addrspace(3)* %ptr5 38 %add5 = fadd float %add4, %val5
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/minix/external/bsd/llvm/dist/llvm/test/CodeGen/Mips/ |
H A D | nacl-reserved-regs.ll | 12 %val5 = load volatile i32* @var 28 store volatile i32 %val5, i32* @var
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H A D | mips16ex.ll | 70 %lpad.val5 = insertvalue { i8*, i32 } %lpad.val, i32 %sel4, 1 71 resume { i8*, i32 } %lpad.val5
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