| /netbsd/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 59 AssertSext, enumerator
|
| /netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 107 case ISD::AssertSext: return "AssertSext"; in getOperationName()
|
| H A D | LegalizeIntegerTypes.cpp | 56 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break; in PromoteIntegerResult()
249 return DAG.getNode(ISD::AssertSext, SDLoc(N), in PromoteIntRes_AssertSext()
623 ISD::AssertZext : ISD::AssertSext, dl, NVT, Res, in PromoteIntRes_FP_TO_XINT()
2071 case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break; in ExpandIntegerResult()
2855 Hi = DAG.getNode(ISD::AssertSext, dl, NVT, Hi, in ExpandIntRes_AssertSext()
2859 Lo = DAG.getNode(ISD::AssertSext, dl, NVT, Lo, DAG.getValueType(EVT)); in ExpandIntRes_AssertSext()
|
| H A D | LegalizeVectorOps.cpp | 711 NewOpc = ISD::AssertSext; in PromoteFP_TO_INT()
|
| H A D | SelectionDAGBuilder.cpp | 880 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl, in getCopyFromRegs()
5478 case ISD::AssertSext: in getUnderlyingArgRegs()
9713 AssertOp = ISD::AssertSext; in LowerCallTo()
10264 AssertOp = ISD::AssertSext; in LowerArguments()
|
| H A D | SelectionDAGISel.cpp | 2857 case ISD::AssertSext: in SelectCodeCommon()
|
| H A D | SelectionDAG.cpp | 3697 case ISD::AssertSext: in ComputeNumSignBits()
5661 case ISD::AssertSext: in getNode()
|
| H A D | DAGCombiner.cpp | 1224 case ISD::AssertSext: in PromoteOperand()
1226 return DAG.getNode(ISD::AssertSext, DL, PVT, Op0, Op.getOperand(1)); in PromoteOperand()
1672 case ISD::AssertSext: in visit()
11538 N0.getOperand(0).getOpcode() == ISD::AssertSext && in visitAssertExt()
|
| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/BPF/ |
| H A D | BPFISelLowering.cpp | 340 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue, in LowerFormalArguments()
|
| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.h | 459 Opc != ISD::CopyFromReg && Opc != ISD::AssertSext && in isDef32()
|
| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 452 Arg = DAG.getNode(ISD::AssertSext, dl, MVT::i32, Arg, in LowerFormalArguments_32()
611 Arg = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Arg, in LowerFormalArguments_64()
1329 RV = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), RV, in LowerCall_64()
|
| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.cpp | 429 Arg = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Arg, in LowerFormalArguments()
777 RV = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), RV, in LowerCall()
|
| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelDAGToDAG.cpp | 1258 if (N.getOpcode() == ISD::AssertSext && in selectSExti32()
|
| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/Lanai/ |
| H A D | LanaiISelLowering.cpp | 471 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue, in LowerCCCArguments()
|
| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.cpp | 661 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, in LowerCCCArguments()
|
| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.cpp | 1177 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, in LowerFormalArguments()
|
| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelDAGToDAG.cpp | 1528 case ISD::AssertSext: in keepsLowBits()
|
| H A D | HexagonISelLowering.cpp | 1061 if (Op.getOpcode() != ISD::AssertSext) in LowerSETCC()
|
| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86InstrCompiler.td | 1356 // up to 64 bits. AssertSext/AssertZext aren't saying anything about the upper
1362 N->getOpcode() != ISD::AssertSext &&
|
| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 3533 Val = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Val, in LowerCallResult()
3584 Val = DAG.getNode(ISD::AssertSext, DL, LocVT, Val, DAG.getValueType(ValVT)); in UnpackFromArgumentSlot()
|
| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 564 setTargetDAGCombine(ISD::AssertSext); in AMDGPUTargetLowering()
4088 case ISD::AssertSext: in PerformDAGCombine()
|
| H A D | SIISelLowering.cpp | 1656 unsigned Opc = Arg->Flags.isZExt() ? ISD::AssertZext : ISD::AssertSext; in convertArgType()
2452 Val = DAG.getNode(ISD::AssertSext, DL, VT, Val, in LowerFormalArguments()
2662 Val = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Val, in LowerCallResult()
|
| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/M68k/ |
| H A D | M68kISelLowering.cpp | 907 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue, in LowerFormalArguments()
|
| /netbsd/external/apache2/llvm/dist/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 704 def assertsext : SDNode<"ISD::AssertSext", SDT_assert>;
|
| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 4197 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal, in extendArgForPPC64()
5128 Val = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), Val, in LowerCallResult()
6773 ArgValue = DAG.getNode(ISD::AssertSext, dl, LocVT, ArgValue, in truncateScalarIntegerArg()
16487 ExtsSrc.getOperand(0).getOpcode() == ISD::AssertSext) in combineSHL()
|