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Searched refs:CONCAT_VECTORS (Results 1 – 24 of 24) sorted by relevance

/netbsd/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp120 setOperationAction(ISD::CONCAT_VECTORS, T, Custom); in initializeHVXLowering()
154 setOperationAction(ISD::CONCAT_VECTORS, T, Custom); in initializeHVXLowering()
224 setOperationAction(ISD::CONCAT_VECTORS, BoolV, Custom); in initializeHVXLowering()
366 return DAG.getNode(ISD::CONCAT_VECTORS, dl, typeJoin(ty(Ops)), in opJoin()
1051 SDValue InLo = DAG.getNode(ISD::CONCAT_VECTORS, dl, VecTy, {SubV, V1}); in insertHvxSubvectorReg()
1244 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VecTy, V0, V1); in LowerHvxBuildVector()
1319 SDValue V0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfTy, in LowerHvxConcatVectors()
1321 SDValue V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfTy, in LowerHvxConcatVectors()
1798 SDValue S = DAG.getNode(ISD::CONCAT_VECTORS, dl, ResTy, L, H); in SplitHvxPairOp()
1831 { DAG.getNode(ISD::CONCAT_VECTORS, dl, MemTy, Load0, Load1), in SplitHvxMemOp()
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H A DHexagonISelLowering.cpp1649 ISD::CONCAT_VECTORS, ISD::VECTOR_SHUFFLE, in HexagonTargetLowering()
1699 setOperationAction(ISD::CONCAT_VECTORS, NativeVT, Custom); in HexagonTargetLowering()
2720 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResTy, Concats); in appendUndef()
3137 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG); in LowerOperation()
H A DHexagonISelDAGToDAGHVX.cpp1481 LV = DAG.getNode(ISD::CONCAT_VECTORS, dl, ResTy, {L0, L1}); in scalarizeShuffle()
/netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorTypes.cpp622 case ISD::CONCAT_VECTORS: in ScalarizeVectorOperand()
1247 Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, LoVT, LoOps); in SplitVecRes_CONCAT_VECTORS()
1250 Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HiVT, HiOps); in SplitVecRes_CONCAT_VECTORS()
1558 ISD::CONCAT_VECTORS, dl, OtherVT, in SplitVecRes_OverflowOp()
2359 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi); in SplitVecOp_UnaryOp()
2932 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi); in SplitVecOp_FP_ROUND()
2955 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi); in SplitVecOp_FP_TO_XINT_SAT()
3270 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, in CollectOpsToWiden()
4154 else if (N.getOpcode() == ISD::CONCAT_VECTORS) { in isSETCCorConvertedSETCC()
5375 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, in GenWidenVectorLoads()
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H A DDAGCombiner.cpp9577 assert(LHS.getOpcode() == ISD::CONCAT_VECTORS && in ConvertSelectToConcatVector()
9578 RHS.getOpcode() == ISD::CONCAT_VECTORS && in ConvertSelectToConcatVector()
9618 ISD::CONCAT_VECTORS, DL, VT, in ConvertSelectToConcatVector()
10071 if (N1.getOpcode() == ISD::CONCAT_VECTORS && in visitVSELECT()
10072 N2.getOpcode() == ISD::CONCAT_VECTORS && in visitVSELECT()
18196 if (ArgVal.getOpcode() == ISD::CONCAT_VECTORS) { in combineInsertEltToShuffle()
19942 if (IndexC && V.getOpcode() == ISD::CONCAT_VECTORS && in getSubVectorSrc()
20252 if (V.getOpcode() == ISD::CONCAT_VECTORS) { in visitEXTRACT_SUBVECTOR()
21028 if (N0.getOpcode() == ISD::CONCAT_VECTORS && in visitVECTOR_SHUFFLE()
21031 (N1.getOpcode() == ISD::CONCAT_VECTORS && in visitVECTOR_SHUFFLE()
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H A DSelectionDAGDumper.cpp286 case ISD::CONCAT_VECTORS: return "concat_vectors"; in getOperationName()
H A DSelectionDAG.cpp2854 case ISD::CONCAT_VECTORS: { in computeKnownBits()
4105 case ISD::CONCAT_VECTORS: { in ComputeNumSignBits()
4801 case ISD::CONCAT_VECTORS: in getNode()
5145 if (Opcode >= ISD::BUILTIN_OP_END || Opcode == ISD::CONCAT_VECTORS) in FoldConstantArithmetic()
5518 case ISD::CONCAT_VECTORS: { in getNode()
5753 N1.getOpcode() == ISD::CONCAT_VECTORS && N1.getNumOperands() > 0) { in getNode()
5866 if (N1.getOpcode() == ISD::CONCAT_VECTORS && N1.getNumOperands() > 0 && in getNode()
6003 case ISD::CONCAT_VECTORS: { in getNode()
7875 case ISD::CONCAT_VECTORS: in getNode()
H A DLegalizeDAG.cpp1428 Node->getOpcode() == ISD::CONCAT_VECTORS) && in ExpandVectorBuildThroughStack()
2987 case ISD::CONCAT_VECTORS: in ExpandNode()
4788 SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, SL, NVT, NewOps); in PromoteNode()
4910 SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, SL, NVT, NewElts); in PromoteNode()
H A DLegalizeIntegerTypes.cpp114 case ISD::CONCAT_VECTORS: in PromoteIntegerResult()
1255 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, EOp1, EOp2); in PromoteIntRes_TRUNCATE()
1491 case ISD::CONCAT_VECTORS: Res = PromoteIntOp_CONCAT_VECTORS(N); break; in PromoteIntegerOperand()
H A DSelectionDAGBuilder.cpp390 Val = DAG.getNode(IntermediateVT.isVector() ? ISD::CONCAT_VECTORS in getCopyFromPartsVector()
3617 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, ConcatOps)); in visitShuffleVector()
3635 Src1 = DAG.getNode(ISD::CONCAT_VECTORS, DL, PaddedVT, MOps1); in visitShuffleVector()
3636 Src2 = DAG.getNode(ISD::CONCAT_VECTORS, DL, PaddedVT, MOps2); in visitShuffleVector()
5484 case ISD::CONCAT_VECTORS: in getUnderlyingArgRegs()
H A DTargetLowering.cpp1109 case ISD::CONCAT_VECTORS: { in SimplifyDemandedBits()
2555 case ISD::CONCAT_VECTORS: { in SimplifyDemandedVectorElts()
/netbsd/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h513 CONCAT_VECTORS, enumerator
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp2009 setTargetDAGCombine(ISD::CONCAT_VECTORS); in X86TargetLowering()
6000 if (N->getOpcode() == ISD::CONCAT_VECTORS) { in collectConcatOps()
6069 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, in splitVectorIntUnary()
8052 if (Opcode == ISD::CONCAT_VECTORS) { in getShuffleScalarElt()
10111 ISD::CONCAT_VECTORS, DL, VT, in createVariablePermute()
13669 case ISD::CONCAT_VECTORS: { in lowerShuffleAsBroadcast()
38235 if (N0.getOpcode() != ISD::CONCAT_VECTORS || in combineShuffleOfConcatUndef()
44478 if (Src.getOpcode() != ISD::CONCAT_VECTORS) in combineScalarAndWithMaskSetcc()
44961 ISD::CONCAT_VECTORS, dl, VT, in combineOr()
44970 ISD::CONCAT_VECTORS, dl, VT, in combineOr()
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp322 setOperationAction(ISD::CONCAT_VECTORS, MVT::v3i32, Custom); in AMDGPUTargetLowering()
323 setOperationAction(ISD::CONCAT_VECTORS, MVT::v3f32, Custom); in AMDGPUTargetLowering()
324 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom); in AMDGPUTargetLowering()
325 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f32, Custom); in AMDGPUTargetLowering()
326 setOperationAction(ISD::CONCAT_VECTORS, MVT::v5i32, Custom); in AMDGPUTargetLowering()
327 setOperationAction(ISD::CONCAT_VECTORS, MVT::v5f32, Custom); in AMDGPUTargetLowering()
328 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom); in AMDGPUTargetLowering()
329 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom); in AMDGPUTargetLowering()
1240 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG); in LowerOperation()
1562 Join = DAG.getNode(ISD::CONCAT_VECTORS, SL, VT, LoLoad, HiLoad); in SplitVectorLoad()
H A DSIISelLowering.cpp261 case ISD::CONCAT_VECTORS: in SITargetLowering()
584 case ISD::CONCAT_VECTORS: in SITargetLowering()
4423 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(Op), VT, OpLo, OpHi); in splitUnaryVectorOp()
4447 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(Op), VT, OpLo, OpHi); in splitBinaryVectorOp()
4471 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(Op), VT, OpLo, OpHi); in splitTernaryVectorOp()
5563 return DAG.getNode(ISD::CONCAT_VECTORS, SL, ResultVT, Pieces); in lowerVECTOR_SHUFFLE()
6384 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Loads); in lowerSBuffer()
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp158 setTargetDAGCombine(ISD::CONCAT_VECTORS); in WebAssemblyTargetLowering()
2195 assert(N->getOpcode() == ISD::CONCAT_VECTORS); in performVectorTruncSatLowCombine()
2249 case ISD::CONCAT_VECTORS: in PerformDAGCombine()
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp896 setTargetDAGCombine(ISD::CONCAT_VECTORS); in AArch64TargetLowering()
1175 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom); in AArch64TargetLowering()
1217 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom); in AArch64TargetLowering()
1253 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom); in AArch64TargetLowering()
1387 setOperationAction(ISD::CONCAT_VECTORS, VT, Legal); in addTypeForNEON()
4552 case ISD::CONCAT_VECTORS: in LowerOperation()
8765 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, V0, V1); in tryFormConcatFromShuffle()
8989 } else if (V.getOpcode() == ISD::CONCAT_VECTORS) { in constructDup()
11614 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, PseudoLoadOps); in LowerSVEStructLoad()
13162 DAG.getNode(ISD::CONCAT_VECTORS, dl, ConcatTy, in performConcatVectorsCombine()
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H A DAArch64InstrFormats.td9243 // intrinsic, represented by CONCAT_VECTORS.
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp185 setOperationAction(ISD::CONCAT_VECTORS, VT, Legal); in addTypeForNEON()
442 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom); in addMVEVectorTypes()
7680 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Lower, Upper); in LowerBUILD_VECTOR()
7818 DAG.getNode(ISD::CONCAT_VECTORS, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
9156 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2); in LowerSDIV()
9193 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2); in LowerUDIV()
11972 SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), ConcatVT, in AddCombineVUZPToVPADDL()
14555 if (Op0.getOpcode() != ISD::CONCAT_VECTORS || in PerformVECTOR_SHUFFLECombine()
14556 Op1.getOpcode() != ISD::CONCAT_VECTORS || in PerformVECTOR_SHUFFLECombine()
14572 SDValue NewConcat = DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT, in PerformVECTOR_SHUFFLECombine()
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp520 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom); in RISCVTargetLowering()
584 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom); in RISCVTargetLowering()
638 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom); in RISCVTargetLowering()
1729 if (V.getOpcode() == ISD::CONCAT_VECTORS) { in lowerVECTOR_SHUFFLE()
2316 case ISD::CONCAT_VECTORS: { in LowerOperation()
/netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp741 setOperationAction(ISD::CONCAT_VECTORS, VT, Expand); in initActions()
/netbsd/external/apache2/llvm/dist/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td678 def concat_vectors : SDNode<"ISD::CONCAT_VECTORS",
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp2171 case ISD::CONCAT_VECTORS: in LowerOperation()
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp8326 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WideVT, Ops); in widenVec()