/netbsd/external/gpl3/gdb/dist/gas/testsuite/gas/m68hc11/ |
H A D | indexed12.s | 49 staa D7-D10,x ; -> staa -17,x (9-bit offset), data seg 50 stab D11-D10,y ; -> stab 128,y (9-bit offset), data seg 51 stab D10-D11,y ; -> stab -128,y (9-bit offset), data seg 57 tst D12-D10,x ; -> tst 255,x (9-bit offset), data seg 58 tst D10-D12,x ; -> tst -255,x (9-bit offset), data seg 59 tst D12-D10+1,x ; -> tst 256,x (16-bit offset), data seg 60 mina D13-D10,x ; -> mina 256,x (16-bit offset) 61 mina D10-D13,x ; -> mina -256,x (9-bit offset) 63 maxa D14-D10,x ; -> maxa 257,x (16-bit offset) 64 maxa D10-D14,x ; -> maxa -257,x (16-bit offset) [all …]
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H A D | indexed12.d | 91 staa D7\-D10,x ; \-> staa \-17,x \(9\-bit offset\), data seg 93 stab D11\-D10,y ; \-> stab 128,y \(9\-bit offset\), data seg 95 stab D10\-D11,y ; \-> stab \-128,y \(9\-bit offset\), data seg 97 stab D11\-D10\+1,y ; \-> stab 129,y \(9\-bit offset\), data seg 106 tst D12\-D10,x ; \-> tst 255,x \(9\-bit offset\), data seg 108 tst D10\-D12,x ; \-> tst \-255,x \(9\-bit offset\), data seg 110 tst D12\-D10\+1,x ; \-> tst 256,x \(16\-bit offset\), data seg 112 mina D13\-D10,x ; \-> mina 256,x \(16\-bit offset\) 115 mina D10\-D13,x ; \-> mina \-256,x \(9\-bit offset\) 118 maxa D14\-D10,x ; \-> maxa 257,x \(16\-bit offset\) [all …]
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/netbsd/external/gpl3/gdb.old/dist/gas/testsuite/gas/m68hc11/ |
H A D | indexed12.s | 49 staa D7-D10,x ; -> staa -17,x (9-bit offset), data seg 50 stab D11-D10,y ; -> stab 128,y (9-bit offset), data seg 51 stab D10-D11,y ; -> stab -128,y (9-bit offset), data seg 57 tst D12-D10,x ; -> tst 255,x (9-bit offset), data seg 58 tst D10-D12,x ; -> tst -255,x (9-bit offset), data seg 59 tst D12-D10+1,x ; -> tst 256,x (16-bit offset), data seg 60 mina D13-D10,x ; -> mina 256,x (16-bit offset) 61 mina D10-D13,x ; -> mina -256,x (9-bit offset) 63 maxa D14-D10,x ; -> maxa 257,x (16-bit offset) 64 maxa D10-D14,x ; -> maxa -257,x (16-bit offset) [all …]
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H A D | indexed12.d | 91 staa D7\-D10,x ; \-> staa \-17,x \(9\-bit offset\), data seg 93 stab D11\-D10,y ; \-> stab 128,y \(9\-bit offset\), data seg 95 stab D10\-D11,y ; \-> stab \-128,y \(9\-bit offset\), data seg 97 stab D11\-D10\+1,y ; \-> stab 129,y \(9\-bit offset\), data seg 106 tst D12\-D10,x ; \-> tst 255,x \(9\-bit offset\), data seg 108 tst D10\-D12,x ; \-> tst \-255,x \(9\-bit offset\), data seg 110 tst D12\-D10\+1,x ; \-> tst 256,x \(16\-bit offset\), data seg 112 mina D13\-D10,x ; \-> mina 256,x \(16\-bit offset\) 115 mina D10\-D13,x ; \-> mina \-256,x \(9\-bit offset\) 118 maxa D14\-D10,x ; \-> maxa 257,x \(16\-bit offset\) [all …]
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/netbsd/external/bsd/pcc/dist/pcc/arch/sparc64/ |
H A D | macdefs.h | 195 #define D10 72 macro 245 { D10, -1 }, { D10, -1 }, { D11, -1 }, { D11, -1 }, \
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/netbsd/sys/external/bsd/gnu-efi/dist/inc/aarch64/ |
H A D | efisetjmp_arch.h | 27 UINT64 D10; member
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
H A D | ARMBaseRegisterInfo.h | 79 case D11: case D10: case D9: case D8: in isARMArea3Register()
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H A D | ARMRegisterInfo.td | 129 def D10 : ARMReg<10, "d10", [S20, S21]>, DwarfRegNum<[266]>; 162 def Q5 : ARMReg< 5, "q5", [D10, D11]>;
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H A D | ARMCallingConv.td | 115 CCIfType<[f64], CCAssignToReg<[D8, D9, D10, D11]>>,
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/AArch64/Utils/ |
H A D | AArch64BaseInfo.h | 121 case AArch64::D10: return AArch64::B10; in getBRegFromDReg() 161 case AArch64::B10: return AArch64::D10; in getDRegFromBReg()
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
H A D | HexagonFrameLowering.h | 95 { Hexagon::R21, -20 }, { Hexagon::R20, -24 }, { Hexagon::D10, -24 }, in getCalleeSavedSpillSlots()
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H A D | HexagonRegisterInfo.td | 122 def D10 : Rd<20, "r21:20", [R20, R21]>, DwarfRegNum<[52]>; 388 (add D11, D10, D9, D8, D3, D2, D1, D0)>;
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/Sparc/ |
H A D | SparcRegisterInfo.td | 207 def D10 : Rd<20, "F20", [F20, F21]>, DwarfRegNum<[82]>; 273 def Q5 : Rq<20, "F20", [D10, D11]>;
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
H A D | AArch64PBQPRegAlloc.cpp | 117 case AArch64::D10: in isOdd()
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H A D | AArch64CallingConvention.td | 390 D8, D9, D10, D11, 402 D8, D9, D10, D11, 467 D8, D9, D10, D11,
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H A D | AArch64SchedPredicates.td | 145 CheckRegOperand<0, D10>,
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/Disassembler/ |
H A D | HexagonDisassembler.cpp | 594 Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11, in DecodeDoubleRegsRegisterClass() 604 Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11}; in DecodeGeneralDoubleLow8RegsRegisterClass()
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/AArch64/MCTargetDesc/ |
H A D | AArch64AsmBackend.cpp | 679 else if (Reg1 == AArch64::D10 && Reg2 == AArch64::D11 && in generateCompactUnwindEncoding()
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H A D | AArch64MCTargetDesc.cpp | 177 {codeview::RegisterId::ARM64_D10, AArch64::D10}, in initLLVMToCVRegMapping()
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/ARM/MCTargetDesc/ |
H A D | ARMMCTargetDesc.cpp | 284 {codeview::RegisterId::ARM_ND10, ARM::D10}, in initLLVMToCVRegMapping()
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H A D | ARMAsmBackend.cpp | 1266 static unsigned FPRCSRegs[] = { ARM::D8, ARM::D10, ARM::D12, ARM::D14 }; in generateCompactUnwindEncoding()
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/Sparc/Disassembler/ |
H A D | SparcDisassembler.cpp | 86 SP::D10, SP::D26, SP::D11, SP::D27,
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/MCTargetDesc/ |
H A D | HexagonMCDuplexInfo.cpp | 690 case Hexagon::D10: in addOps()
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H A D | HexagonMCInstrInfo.cpp | 279 case D10: in getDuplexRegisterNumbering()
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
H A D | MipsRegisterInfo.td | 409 D10, D11, D12, D13, D14, D15)>;
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