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Searched refs:D10 (Results 1 – 25 of 45) sorted by relevance

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/netbsd/external/gpl3/gdb/dist/gas/testsuite/gas/m68hc11/
H A Dindexed12.s49 staa D7-D10,x ; -> staa -17,x (9-bit offset), data seg
50 stab D11-D10,y ; -> stab 128,y (9-bit offset), data seg
51 stab D10-D11,y ; -> stab -128,y (9-bit offset), data seg
57 tst D12-D10,x ; -> tst 255,x (9-bit offset), data seg
58 tst D10-D12,x ; -> tst -255,x (9-bit offset), data seg
59 tst D12-D10+1,x ; -> tst 256,x (16-bit offset), data seg
60 mina D13-D10,x ; -> mina 256,x (16-bit offset)
61 mina D10-D13,x ; -> mina -256,x (9-bit offset)
63 maxa D14-D10,x ; -> maxa 257,x (16-bit offset)
64 maxa D10-D14,x ; -> maxa -257,x (16-bit offset)
[all …]
H A Dindexed12.d91 staa D7\-D10,x ; \-> staa \-17,x \(9\-bit offset\), data seg
93 stab D11\-D10,y ; \-> stab 128,y \(9\-bit offset\), data seg
95 stab D10\-D11,y ; \-> stab \-128,y \(9\-bit offset\), data seg
97 stab D11\-D10\+1,y ; \-> stab 129,y \(9\-bit offset\), data seg
106 tst D12\-D10,x ; \-> tst 255,x \(9\-bit offset\), data seg
108 tst D10\-D12,x ; \-> tst \-255,x \(9\-bit offset\), data seg
110 tst D12\-D10\+1,x ; \-> tst 256,x \(16\-bit offset\), data seg
112 mina D13\-D10,x ; \-> mina 256,x \(16\-bit offset\)
115 mina D10\-D13,x ; \-> mina \-256,x \(9\-bit offset\)
118 maxa D14\-D10,x ; \-> maxa 257,x \(16\-bit offset\)
[all …]
/netbsd/external/gpl3/gdb.old/dist/gas/testsuite/gas/m68hc11/
H A Dindexed12.s49 staa D7-D10,x ; -> staa -17,x (9-bit offset), data seg
50 stab D11-D10,y ; -> stab 128,y (9-bit offset), data seg
51 stab D10-D11,y ; -> stab -128,y (9-bit offset), data seg
57 tst D12-D10,x ; -> tst 255,x (9-bit offset), data seg
58 tst D10-D12,x ; -> tst -255,x (9-bit offset), data seg
59 tst D12-D10+1,x ; -> tst 256,x (16-bit offset), data seg
60 mina D13-D10,x ; -> mina 256,x (16-bit offset)
61 mina D10-D13,x ; -> mina -256,x (9-bit offset)
63 maxa D14-D10,x ; -> maxa 257,x (16-bit offset)
64 maxa D10-D14,x ; -> maxa -257,x (16-bit offset)
[all …]
H A Dindexed12.d91 staa D7\-D10,x ; \-> staa \-17,x \(9\-bit offset\), data seg
93 stab D11\-D10,y ; \-> stab 128,y \(9\-bit offset\), data seg
95 stab D10\-D11,y ; \-> stab \-128,y \(9\-bit offset\), data seg
97 stab D11\-D10\+1,y ; \-> stab 129,y \(9\-bit offset\), data seg
106 tst D12\-D10,x ; \-> tst 255,x \(9\-bit offset\), data seg
108 tst D10\-D12,x ; \-> tst \-255,x \(9\-bit offset\), data seg
110 tst D12\-D10\+1,x ; \-> tst 256,x \(16\-bit offset\), data seg
112 mina D13\-D10,x ; \-> mina 256,x \(16\-bit offset\)
115 mina D10\-D13,x ; \-> mina \-256,x \(9\-bit offset\)
118 maxa D14\-D10,x ; \-> maxa 257,x \(16\-bit offset\)
[all …]
/netbsd/external/bsd/pcc/dist/pcc/arch/sparc64/
H A Dmacdefs.h195 #define D10 72 macro
245 { D10, -1 }, { D10, -1 }, { D11, -1 }, { D11, -1 }, \
/netbsd/sys/external/bsd/gnu-efi/dist/inc/aarch64/
H A Defisetjmp_arch.h27 UINT64 D10; member
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMBaseRegisterInfo.h79 case D11: case D10: case D9: case D8: in isARMArea3Register()
H A DARMRegisterInfo.td129 def D10 : ARMReg<10, "d10", [S20, S21]>, DwarfRegNum<[266]>;
162 def Q5 : ARMReg< 5, "q5", [D10, D11]>;
H A DARMCallingConv.td115 CCIfType<[f64], CCAssignToReg<[D8, D9, D10, D11]>>,
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/AArch64/Utils/
H A DAArch64BaseInfo.h121 case AArch64::D10: return AArch64::B10; in getBRegFromDReg()
161 case AArch64::B10: return AArch64::D10; in getDRegFromBReg()
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonFrameLowering.h95 { Hexagon::R21, -20 }, { Hexagon::R20, -24 }, { Hexagon::D10, -24 }, in getCalleeSavedSpillSlots()
H A DHexagonRegisterInfo.td122 def D10 : Rd<20, "r21:20", [R20, R21]>, DwarfRegNum<[52]>;
388 (add D11, D10, D9, D8, D3, D2, D1, D0)>;
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/Sparc/
H A DSparcRegisterInfo.td207 def D10 : Rd<20, "F20", [F20, F21]>, DwarfRegNum<[82]>;
273 def Q5 : Rq<20, "F20", [D10, D11]>;
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64PBQPRegAlloc.cpp117 case AArch64::D10: in isOdd()
H A DAArch64CallingConvention.td390 D8, D9, D10, D11,
402 D8, D9, D10, D11,
467 D8, D9, D10, D11,
H A DAArch64SchedPredicates.td145 CheckRegOperand<0, D10>,
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/Disassembler/
H A DHexagonDisassembler.cpp594 Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11, in DecodeDoubleRegsRegisterClass()
604 Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11}; in DecodeGeneralDoubleLow8RegsRegisterClass()
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64AsmBackend.cpp679 else if (Reg1 == AArch64::D10 && Reg2 == AArch64::D11 && in generateCompactUnwindEncoding()
H A DAArch64MCTargetDesc.cpp177 {codeview::RegisterId::ARM64_D10, AArch64::D10}, in initLLVMToCVRegMapping()
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMMCTargetDesc.cpp284 {codeview::RegisterId::ARM_ND10, ARM::D10}, in initLLVMToCVRegMapping()
H A DARMAsmBackend.cpp1266 static unsigned FPRCSRegs[] = { ARM::D8, ARM::D10, ARM::D12, ARM::D14 }; in generateCompactUnwindEncoding()
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/Sparc/Disassembler/
H A DSparcDisassembler.cpp86 SP::D10, SP::D26, SP::D11, SP::D27,
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCDuplexInfo.cpp690 case Hexagon::D10: in addOps()
H A DHexagonMCInstrInfo.cpp279 case D10: in getDuplexRegisterNumbering()
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/Mips/
H A DMipsRegisterInfo.td409 D10, D11, D12, D13, D14, D15)>;

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