1 /*	$NetBSD: drm_fourcc.h,v 1.2 2021/12/18 23:45:46 riastradh Exp $	*/
2 
3 /*
4  * Copyright 2011 Intel Corporation
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice (including the next
14  * paragraph) shall be included in all copies or substantial portions of the
15  * Software.
16  *
17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
20  * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
21  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
22  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
23  * OTHER DEALINGS IN THE SOFTWARE.
24  */
25 
26 #ifndef DRM_FOURCC_H
27 #define DRM_FOURCC_H
28 
29 #include "drm.h"
30 
31 #if defined(__cplusplus)
32 extern "C" {
33 #endif
34 
35 /**
36  * DOC: overview
37  *
38  * In the DRM subsystem, framebuffer pixel formats are described using the
39  * fourcc codes defined in `include/uapi/drm/drm_fourcc.h`. In addition to the
40  * fourcc code, a Format Modifier may optionally be provided, in order to
41  * further describe the buffer's format - for example tiling or compression.
42  *
43  * Format Modifiers
44  * ----------------
45  *
46  * Format modifiers are used in conjunction with a fourcc code, forming a
47  * unique fourcc:modifier pair. This format:modifier pair must fully define the
48  * format and data layout of the buffer, and should be the only way to describe
49  * that particular buffer.
50  *
51  * Having multiple fourcc:modifier pairs which describe the same layout should
52  * be avoided, as such aliases run the risk of different drivers exposing
53  * different names for the same data format, forcing userspace to understand
54  * that they are aliases.
55  *
56  * Format modifiers may change any property of the buffer, including the number
57  * of planes and/or the required allocation size. Format modifiers are
58  * vendor-namespaced, and as such the relationship between a fourcc code and a
59  * modifier is specific to the modifer being used. For example, some modifiers
60  * may preserve meaning - such as number of planes - from the fourcc code,
61  * whereas others may not.
62  *
63  * Vendors should document their modifier usage in as much detail as
64  * possible, to ensure maximum compatibility across devices, drivers and
65  * applications.
66  *
67  * The authoritative list of format modifier codes is found in
68  * `include/uapi/drm/drm_fourcc.h`
69  */
70 
71 #define fourcc_code(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) | \
72 				 ((__u32)(c) << 16) | ((__u32)(d) << 24))
73 
74 #define DRM_FORMAT_BIG_ENDIAN (1U<<31) /* format is big endian instead of little endian */
75 
76 /* Reserve 0 for the invalid format specifier */
77 #define DRM_FORMAT_INVALID	0
78 
79 /* color index */
80 #define DRM_FORMAT_C8		fourcc_code('C', '8', ' ', ' ') /* [7:0] C */
81 
82 /* 8 bpp Red */
83 #define DRM_FORMAT_R8		fourcc_code('R', '8', ' ', ' ') /* [7:0] R */
84 
85 /* 16 bpp Red */
86 #define DRM_FORMAT_R16		fourcc_code('R', '1', '6', ' ') /* [15:0] R little endian */
87 
88 /* 16 bpp RG */
89 #define DRM_FORMAT_RG88		fourcc_code('R', 'G', '8', '8') /* [15:0] R:G 8:8 little endian */
90 #define DRM_FORMAT_GR88		fourcc_code('G', 'R', '8', '8') /* [15:0] G:R 8:8 little endian */
91 
92 /* 32 bpp RG */
93 #define DRM_FORMAT_RG1616	fourcc_code('R', 'G', '3', '2') /* [31:0] R:G 16:16 little endian */
94 #define DRM_FORMAT_GR1616	fourcc_code('G', 'R', '3', '2') /* [31:0] G:R 16:16 little endian */
95 
96 /* 8 bpp RGB */
97 #define DRM_FORMAT_RGB332	fourcc_code('R', 'G', 'B', '8') /* [7:0] R:G:B 3:3:2 */
98 #define DRM_FORMAT_BGR233	fourcc_code('B', 'G', 'R', '8') /* [7:0] B:G:R 2:3:3 */
99 
100 /* 16 bpp RGB */
101 #define DRM_FORMAT_XRGB4444	fourcc_code('X', 'R', '1', '2') /* [15:0] x:R:G:B 4:4:4:4 little endian */
102 #define DRM_FORMAT_XBGR4444	fourcc_code('X', 'B', '1', '2') /* [15:0] x:B:G:R 4:4:4:4 little endian */
103 #define DRM_FORMAT_RGBX4444	fourcc_code('R', 'X', '1', '2') /* [15:0] R:G:B:x 4:4:4:4 little endian */
104 #define DRM_FORMAT_BGRX4444	fourcc_code('B', 'X', '1', '2') /* [15:0] B:G:R:x 4:4:4:4 little endian */
105 
106 #define DRM_FORMAT_ARGB4444	fourcc_code('A', 'R', '1', '2') /* [15:0] A:R:G:B 4:4:4:4 little endian */
107 #define DRM_FORMAT_ABGR4444	fourcc_code('A', 'B', '1', '2') /* [15:0] A:B:G:R 4:4:4:4 little endian */
108 #define DRM_FORMAT_RGBA4444	fourcc_code('R', 'A', '1', '2') /* [15:0] R:G:B:A 4:4:4:4 little endian */
109 #define DRM_FORMAT_BGRA4444	fourcc_code('B', 'A', '1', '2') /* [15:0] B:G:R:A 4:4:4:4 little endian */
110 
111 #define DRM_FORMAT_XRGB1555	fourcc_code('X', 'R', '1', '5') /* [15:0] x:R:G:B 1:5:5:5 little endian */
112 #define DRM_FORMAT_XBGR1555	fourcc_code('X', 'B', '1', '5') /* [15:0] x:B:G:R 1:5:5:5 little endian */
113 #define DRM_FORMAT_RGBX5551	fourcc_code('R', 'X', '1', '5') /* [15:0] R:G:B:x 5:5:5:1 little endian */
114 #define DRM_FORMAT_BGRX5551	fourcc_code('B', 'X', '1', '5') /* [15:0] B:G:R:x 5:5:5:1 little endian */
115 
116 #define DRM_FORMAT_ARGB1555	fourcc_code('A', 'R', '1', '5') /* [15:0] A:R:G:B 1:5:5:5 little endian */
117 #define DRM_FORMAT_ABGR1555	fourcc_code('A', 'B', '1', '5') /* [15:0] A:B:G:R 1:5:5:5 little endian */
118 #define DRM_FORMAT_RGBA5551	fourcc_code('R', 'A', '1', '5') /* [15:0] R:G:B:A 5:5:5:1 little endian */
119 #define DRM_FORMAT_BGRA5551	fourcc_code('B', 'A', '1', '5') /* [15:0] B:G:R:A 5:5:5:1 little endian */
120 
121 #define DRM_FORMAT_RGB565	fourcc_code('R', 'G', '1', '6') /* [15:0] R:G:B 5:6:5 little endian */
122 #define DRM_FORMAT_BGR565	fourcc_code('B', 'G', '1', '6') /* [15:0] B:G:R 5:6:5 little endian */
123 
124 /* 24 bpp RGB */
125 #define DRM_FORMAT_RGB888	fourcc_code('R', 'G', '2', '4') /* [23:0] R:G:B little endian */
126 #define DRM_FORMAT_BGR888	fourcc_code('B', 'G', '2', '4') /* [23:0] B:G:R little endian */
127 
128 /* 32 bpp RGB */
129 #define DRM_FORMAT_XRGB8888	fourcc_code('X', 'R', '2', '4') /* [31:0] x:R:G:B 8:8:8:8 little endian */
130 #define DRM_FORMAT_XBGR8888	fourcc_code('X', 'B', '2', '4') /* [31:0] x:B:G:R 8:8:8:8 little endian */
131 #define DRM_FORMAT_RGBX8888	fourcc_code('R', 'X', '2', '4') /* [31:0] R:G:B:x 8:8:8:8 little endian */
132 #define DRM_FORMAT_BGRX8888	fourcc_code('B', 'X', '2', '4') /* [31:0] B:G:R:x 8:8:8:8 little endian */
133 
134 #define DRM_FORMAT_ARGB8888	fourcc_code('A', 'R', '2', '4') /* [31:0] A:R:G:B 8:8:8:8 little endian */
135 #define DRM_FORMAT_ABGR8888	fourcc_code('A', 'B', '2', '4') /* [31:0] A:B:G:R 8:8:8:8 little endian */
136 #define DRM_FORMAT_RGBA8888	fourcc_code('R', 'A', '2', '4') /* [31:0] R:G:B:A 8:8:8:8 little endian */
137 #define DRM_FORMAT_BGRA8888	fourcc_code('B', 'A', '2', '4') /* [31:0] B:G:R:A 8:8:8:8 little endian */
138 
139 #define DRM_FORMAT_XRGB2101010	fourcc_code('X', 'R', '3', '0') /* [31:0] x:R:G:B 2:10:10:10 little endian */
140 #define DRM_FORMAT_XBGR2101010	fourcc_code('X', 'B', '3', '0') /* [31:0] x:B:G:R 2:10:10:10 little endian */
141 #define DRM_FORMAT_RGBX1010102	fourcc_code('R', 'X', '3', '0') /* [31:0] R:G:B:x 10:10:10:2 little endian */
142 #define DRM_FORMAT_BGRX1010102	fourcc_code('B', 'X', '3', '0') /* [31:0] B:G:R:x 10:10:10:2 little endian */
143 
144 #define DRM_FORMAT_ARGB2101010	fourcc_code('A', 'R', '3', '0') /* [31:0] A:R:G:B 2:10:10:10 little endian */
145 #define DRM_FORMAT_ABGR2101010	fourcc_code('A', 'B', '3', '0') /* [31:0] A:B:G:R 2:10:10:10 little endian */
146 #define DRM_FORMAT_RGBA1010102	fourcc_code('R', 'A', '3', '0') /* [31:0] R:G:B:A 10:10:10:2 little endian */
147 #define DRM_FORMAT_BGRA1010102	fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little endian */
148 
149 /*
150  * Floating point 64bpp RGB
151  * IEEE 754-2008 binary16 half-precision float
152  * [15:0] sign:exponent:mantissa 1:5:10
153  */
154 #define DRM_FORMAT_XRGB16161616F fourcc_code('X', 'R', '4', 'H') /* [63:0] x:R:G:B 16:16:16:16 little endian */
155 #define DRM_FORMAT_XBGR16161616F fourcc_code('X', 'B', '4', 'H') /* [63:0] x:B:G:R 16:16:16:16 little endian */
156 
157 #define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 little endian */
158 #define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 little endian */
159 
160 /* packed YCbCr */
161 #define DRM_FORMAT_YUYV		fourcc_code('Y', 'U', 'Y', 'V') /* [31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little endian */
162 #define DRM_FORMAT_YVYU		fourcc_code('Y', 'V', 'Y', 'U') /* [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little endian */
163 #define DRM_FORMAT_UYVY		fourcc_code('U', 'Y', 'V', 'Y') /* [31:0] Y1:Cr0:Y0:Cb0 8:8:8:8 little endian */
164 #define DRM_FORMAT_VYUY		fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */
165 
166 #define DRM_FORMAT_AYUV		fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
167 #define DRM_FORMAT_XYUV8888	fourcc_code('X', 'Y', 'U', 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */
168 #define DRM_FORMAT_VUY888	fourcc_code('V', 'U', '2', '4') /* [23:0] Cr:Cb:Y 8:8:8 little endian */
169 #define DRM_FORMAT_VUY101010	fourcc_code('V', 'U', '3', '0') /* Y followed by U then V, 10:10:10. Non-linear modifier only */
170 
171 /*
172  * packed Y2xx indicate for each component, xx valid data occupy msb
173  * 16-xx padding occupy lsb
174  */
175 #define DRM_FORMAT_Y210         fourcc_code('Y', '2', '1', '0') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 10:6:10:6:10:6:10:6 little endian per 2 Y pixels */
176 #define DRM_FORMAT_Y212         fourcc_code('Y', '2', '1', '2') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 12:4:12:4:12:4:12:4 little endian per 2 Y pixels */
177 #define DRM_FORMAT_Y216         fourcc_code('Y', '2', '1', '6') /* [63:0] Cr0:Y1:Cb0:Y0 16:16:16:16 little endian per 2 Y pixels */
178 
179 /*
180  * packed Y4xx indicate for each component, xx valid data occupy msb
181  * 16-xx padding occupy lsb except Y410
182  */
183 #define DRM_FORMAT_Y410         fourcc_code('Y', '4', '1', '0') /* [31:0] A:Cr:Y:Cb 2:10:10:10 little endian */
184 #define DRM_FORMAT_Y412         fourcc_code('Y', '4', '1', '2') /* [63:0] A:0:Cr:0:Y:0:Cb:0 12:4:12:4:12:4:12:4 little endian */
185 #define DRM_FORMAT_Y416         fourcc_code('Y', '4', '1', '6') /* [63:0] A:Cr:Y:Cb 16:16:16:16 little endian */
186 
187 #define DRM_FORMAT_XVYU2101010	fourcc_code('X', 'V', '3', '0') /* [31:0] X:Cr:Y:Cb 2:10:10:10 little endian */
188 #define DRM_FORMAT_XVYU12_16161616	fourcc_code('X', 'V', '3', '6') /* [63:0] X:0:Cr:0:Y:0:Cb:0 12:4:12:4:12:4:12:4 little endian */
189 #define DRM_FORMAT_XVYU16161616	fourcc_code('X', 'V', '4', '8') /* [63:0] X:Cr:Y:Cb 16:16:16:16 little endian */
190 
191 /*
192  * packed YCbCr420 2x2 tiled formats
193  * first 64 bits will contain Y,Cb,Cr components for a 2x2 tile
194  */
195 /* [63:0]   A3:A2:Y3:0:Cr0:0:Y2:0:A1:A0:Y1:0:Cb0:0:Y0:0  1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */
196 #define DRM_FORMAT_Y0L0		fourcc_code('Y', '0', 'L', '0')
197 /* [63:0]   X3:X2:Y3:0:Cr0:0:Y2:0:X1:X0:Y1:0:Cb0:0:Y0:0  1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */
198 #define DRM_FORMAT_X0L0		fourcc_code('X', '0', 'L', '0')
199 
200 /* [63:0]   A3:A2:Y3:Cr0:Y2:A1:A0:Y1:Cb0:Y0  1:1:10:10:10:1:1:10:10:10 little endian */
201 #define DRM_FORMAT_Y0L2		fourcc_code('Y', '0', 'L', '2')
202 /* [63:0]   X3:X2:Y3:Cr0:Y2:X1:X0:Y1:Cb0:Y0  1:1:10:10:10:1:1:10:10:10 little endian */
203 #define DRM_FORMAT_X0L2		fourcc_code('X', '0', 'L', '2')
204 
205 /*
206  * 1-plane YUV 4:2:0
207  * In these formats, the component ordering is specified (Y, followed by U
208  * then V), but the exact Linear layout is undefined.
209  * These formats can only be used with a non-Linear modifier.
210  */
211 #define DRM_FORMAT_YUV420_8BIT	fourcc_code('Y', 'U', '0', '8')
212 #define DRM_FORMAT_YUV420_10BIT	fourcc_code('Y', 'U', '1', '0')
213 
214 /*
215  * 2 plane RGB + A
216  * index 0 = RGB plane, same format as the corresponding non _A8 format has
217  * index 1 = A plane, [7:0] A
218  */
219 #define DRM_FORMAT_XRGB8888_A8	fourcc_code('X', 'R', 'A', '8')
220 #define DRM_FORMAT_XBGR8888_A8	fourcc_code('X', 'B', 'A', '8')
221 #define DRM_FORMAT_RGBX8888_A8	fourcc_code('R', 'X', 'A', '8')
222 #define DRM_FORMAT_BGRX8888_A8	fourcc_code('B', 'X', 'A', '8')
223 #define DRM_FORMAT_RGB888_A8	fourcc_code('R', '8', 'A', '8')
224 #define DRM_FORMAT_BGR888_A8	fourcc_code('B', '8', 'A', '8')
225 #define DRM_FORMAT_RGB565_A8	fourcc_code('R', '5', 'A', '8')
226 #define DRM_FORMAT_BGR565_A8	fourcc_code('B', '5', 'A', '8')
227 
228 /*
229  * 2 plane YCbCr
230  * index 0 = Y plane, [7:0] Y
231  * index 1 = Cr:Cb plane, [15:0] Cr:Cb little endian
232  * or
233  * index 1 = Cb:Cr plane, [15:0] Cb:Cr little endian
234  */
235 #define DRM_FORMAT_NV12		fourcc_code('N', 'V', '1', '2') /* 2x2 subsampled Cr:Cb plane */
236 #define DRM_FORMAT_NV21		fourcc_code('N', 'V', '2', '1') /* 2x2 subsampled Cb:Cr plane */
237 #define DRM_FORMAT_NV16		fourcc_code('N', 'V', '1', '6') /* 2x1 subsampled Cr:Cb plane */
238 #define DRM_FORMAT_NV61		fourcc_code('N', 'V', '6', '1') /* 2x1 subsampled Cb:Cr plane */
239 #define DRM_FORMAT_NV24		fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */
240 #define DRM_FORMAT_NV42		fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
241 
242 /*
243  * 2 plane YCbCr MSB aligned
244  * index 0 = Y plane, [15:0] Y:x [10:6] little endian
245  * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian
246  */
247 #define DRM_FORMAT_P210		fourcc_code('P', '2', '1', '0') /* 2x1 subsampled Cr:Cb plane, 10 bit per channel */
248 
249 /*
250  * 2 plane YCbCr MSB aligned
251  * index 0 = Y plane, [15:0] Y:x [10:6] little endian
252  * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian
253  */
254 #define DRM_FORMAT_P010		fourcc_code('P', '0', '1', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per channel */
255 
256 /*
257  * 2 plane YCbCr MSB aligned
258  * index 0 = Y plane, [15:0] Y:x [12:4] little endian
259  * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [12:4:12:4] little endian
260  */
261 #define DRM_FORMAT_P012		fourcc_code('P', '0', '1', '2') /* 2x2 subsampled Cr:Cb plane 12 bits per channel */
262 
263 /*
264  * 2 plane YCbCr MSB aligned
265  * index 0 = Y plane, [15:0] Y little endian
266  * index 1 = Cr:Cb plane, [31:0] Cr:Cb [16:16] little endian
267  */
268 #define DRM_FORMAT_P016		fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cr:Cb plane 16 bits per channel */
269 
270 /*
271  * 3 plane YCbCr
272  * index 0: Y plane, [7:0] Y
273  * index 1: Cb plane, [7:0] Cb
274  * index 2: Cr plane, [7:0] Cr
275  * or
276  * index 1: Cr plane, [7:0] Cr
277  * index 2: Cb plane, [7:0] Cb
278  */
279 #define DRM_FORMAT_YUV410	fourcc_code('Y', 'U', 'V', '9') /* 4x4 subsampled Cb (1) and Cr (2) planes */
280 #define DRM_FORMAT_YVU410	fourcc_code('Y', 'V', 'U', '9') /* 4x4 subsampled Cr (1) and Cb (2) planes */
281 #define DRM_FORMAT_YUV411	fourcc_code('Y', 'U', '1', '1') /* 4x1 subsampled Cb (1) and Cr (2) planes */
282 #define DRM_FORMAT_YVU411	fourcc_code('Y', 'V', '1', '1') /* 4x1 subsampled Cr (1) and Cb (2) planes */
283 #define DRM_FORMAT_YUV420	fourcc_code('Y', 'U', '1', '2') /* 2x2 subsampled Cb (1) and Cr (2) planes */
284 #define DRM_FORMAT_YVU420	fourcc_code('Y', 'V', '1', '2') /* 2x2 subsampled Cr (1) and Cb (2) planes */
285 #define DRM_FORMAT_YUV422	fourcc_code('Y', 'U', '1', '6') /* 2x1 subsampled Cb (1) and Cr (2) planes */
286 #define DRM_FORMAT_YVU422	fourcc_code('Y', 'V', '1', '6') /* 2x1 subsampled Cr (1) and Cb (2) planes */
287 #define DRM_FORMAT_YUV444	fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) planes */
288 #define DRM_FORMAT_YVU444	fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) planes */
289 
290 
291 /*
292  * Format Modifiers:
293  *
294  * Format modifiers describe, typically, a re-ordering or modification
295  * of the data in a plane of an FB.  This can be used to express tiled/
296  * swizzled formats, or compression, or a combination of the two.
297  *
298  * The upper 8 bits of the format modifier are a vendor-id as assigned
299  * below.  The lower 56 bits are assigned as vendor sees fit.
300  */
301 
302 /* Vendor Ids: */
303 #define DRM_FORMAT_MOD_NONE           0
304 #define DRM_FORMAT_MOD_VENDOR_NONE    0
305 #define DRM_FORMAT_MOD_VENDOR_INTEL   0x01
306 #define DRM_FORMAT_MOD_VENDOR_AMD     0x02
307 #define DRM_FORMAT_MOD_VENDOR_NVIDIA  0x03
308 #define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04
309 #define DRM_FORMAT_MOD_VENDOR_QCOM    0x05
310 #define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06
311 #define DRM_FORMAT_MOD_VENDOR_BROADCOM 0x07
312 #define DRM_FORMAT_MOD_VENDOR_ARM     0x08
313 #define DRM_FORMAT_MOD_VENDOR_ALLWINNER 0x09
314 
315 /* add more to the end as needed */
316 
317 #define DRM_FORMAT_RESERVED	      ((1ULL << 56) - 1)
318 
319 #define fourcc_mod_code(vendor, val) \
320 	((((__u64)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | ((val) & 0x00ffffffffffffffULL))
321 
322 /*
323  * Format Modifier tokens:
324  *
325  * When adding a new token please document the layout with a code comment,
326  * similar to the fourcc codes above. drm_fourcc.h is considered the
327  * authoritative source for all of these.
328  */
329 
330 /*
331  * Invalid Modifier
332  *
333  * This modifier can be used as a sentinel to terminate the format modifiers
334  * list, or to initialize a variable with an invalid modifier. It might also be
335  * used to report an error back to userspace for certain APIs.
336  */
337 #define DRM_FORMAT_MOD_INVALID	fourcc_mod_code(NONE, DRM_FORMAT_RESERVED)
338 
339 /*
340  * Linear Layout
341  *
342  * Just plain linear layout. Note that this is different from no specifying any
343  * modifier (e.g. not setting DRM_MODE_FB_MODIFIERS in the DRM_ADDFB2 ioctl),
344  * which tells the driver to also take driver-internal information into account
345  * and so might actually result in a tiled framebuffer.
346  */
347 #define DRM_FORMAT_MOD_LINEAR	fourcc_mod_code(NONE, 0)
348 
349 /* Intel framebuffer modifiers */
350 
351 /*
352  * Intel X-tiling layout
353  *
354  * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
355  * in row-major layout. Within the tile bytes are laid out row-major, with
356  * a platform-dependent stride. On top of that the memory can apply
357  * platform-depending swizzling of some higher address bits into bit6.
358  *
359  * This format is highly platforms specific and not useful for cross-driver
360  * sharing. It exists since on a given platform it does uniquely identify the
361  * layout in a simple way for i915-specific userspace.
362  */
363 #define I915_FORMAT_MOD_X_TILED	fourcc_mod_code(INTEL, 1)
364 
365 /*
366  * Intel Y-tiling layout
367  *
368  * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
369  * in row-major layout. Within the tile bytes are laid out in OWORD (16 bytes)
370  * chunks column-major, with a platform-dependent height. On top of that the
371  * memory can apply platform-depending swizzling of some higher address bits
372  * into bit6.
373  *
374  * This format is highly platforms specific and not useful for cross-driver
375  * sharing. It exists since on a given platform it does uniquely identify the
376  * layout in a simple way for i915-specific userspace.
377  */
378 #define I915_FORMAT_MOD_Y_TILED	fourcc_mod_code(INTEL, 2)
379 
380 /*
381  * Intel Yf-tiling layout
382  *
383  * This is a tiled layout using 4Kb tiles in row-major layout.
384  * Within the tile pixels are laid out in 16 256 byte units / sub-tiles which
385  * are arranged in four groups (two wide, two high) with column-major layout.
386  * Each group therefore consits out of four 256 byte units, which are also laid
387  * out as 2x2 column-major.
388  * 256 byte units are made out of four 64 byte blocks of pixels, producing
389  * either a square block or a 2:1 unit.
390  * 64 byte blocks of pixels contain four pixel rows of 16 bytes, where the width
391  * in pixel depends on the pixel depth.
392  */
393 #define I915_FORMAT_MOD_Yf_TILED fourcc_mod_code(INTEL, 3)
394 
395 /*
396  * Intel color control surface (CCS) for render compression
397  *
398  * The framebuffer format must be one of the 8:8:8:8 RGB formats.
399  * The main surface will be plane index 0 and must be Y/Yf-tiled,
400  * the CCS will be plane index 1.
401  *
402  * Each CCS tile matches a 1024x512 pixel area of the main surface.
403  * To match certain aspects of the 3D hardware the CCS is
404  * considered to be made up of normal 128Bx32 Y tiles, Thus
405  * the CCS pitch must be specified in multiples of 128 bytes.
406  *
407  * In reality the CCS tile appears to be a 64Bx64 Y tile, composed
408  * of QWORD (8 bytes) chunks instead of OWORD (16 bytes) chunks.
409  * But that fact is not relevant unless the memory is accessed
410  * directly.
411  */
412 #define I915_FORMAT_MOD_Y_TILED_CCS	fourcc_mod_code(INTEL, 4)
413 #define I915_FORMAT_MOD_Yf_TILED_CCS	fourcc_mod_code(INTEL, 5)
414 
415 /*
416  * Intel color control surfaces (CCS) for Gen-12 render compression.
417  *
418  * The main surface is Y-tiled and at plane index 0, the CCS is linear and
419  * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
420  * main surface. In other words, 4 bits in CCS map to a main surface cache
421  * line pair. The main surface pitch is required to be a multiple of four
422  * Y-tile widths.
423  */
424 #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6)
425 
426 /*
427  * Intel color control surfaces (CCS) for Gen-12 media compression
428  *
429  * The main surface is Y-tiled and at plane index 0, the CCS is linear and
430  * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
431  * main surface. In other words, 4 bits in CCS map to a main surface cache
432  * line pair. The main surface pitch is required to be a multiple of four
433  * Y-tile widths. For semi-planar formats like NV12, CCS planes follow the
434  * Y and UV planes i.e., planes 0 and 1 are used for Y and UV surfaces,
435  * planes 2 and 3 for the respective CCS.
436  */
437 #define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7)
438 
439 /*
440  * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
441  *
442  * Macroblocks are laid in a Z-shape, and each pixel data is following the
443  * standard NV12 style.
444  * As for NV12, an image is the result of two frame buffers: one for Y,
445  * one for the interleaved Cb/Cr components (1/2 the height of the Y buffer).
446  * Alignment requirements are (for each buffer):
447  * - multiple of 128 pixels for the width
448  * - multiple of  32 pixels for the height
449  *
450  * For more information: see https://linuxtv.org/downloads/v4l-dvb-apis/re32.html
451  */
452 #define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE	fourcc_mod_code(SAMSUNG, 1)
453 
454 /*
455  * Tiled, 16 (pixels) x 16 (lines) - sized macroblocks
456  *
457  * This is a simple tiled layout using tiles of 16x16 pixels in a row-major
458  * layout. For YCbCr formats Cb/Cr components are taken in such a way that
459  * they correspond to their 16x16 luma block.
460  */
461 #define DRM_FORMAT_MOD_SAMSUNG_16_16_TILE	fourcc_mod_code(SAMSUNG, 2)
462 
463 /*
464  * Qualcomm Compressed Format
465  *
466  * Refers to a compressed variant of the base format that is compressed.
467  * Implementation may be platform and base-format specific.
468  *
469  * Each macrotile consists of m x n (mostly 4 x 4) tiles.
470  * Pixel data pitch/stride is aligned with macrotile width.
471  * Pixel data height is aligned with macrotile height.
472  * Entire pixel data buffer is aligned with 4k(bytes).
473  */
474 #define DRM_FORMAT_MOD_QCOM_COMPRESSED	fourcc_mod_code(QCOM, 1)
475 
476 /* Vivante framebuffer modifiers */
477 
478 /*
479  * Vivante 4x4 tiling layout
480  *
481  * This is a simple tiled layout using tiles of 4x4 pixels in a row-major
482  * layout.
483  */
484 #define DRM_FORMAT_MOD_VIVANTE_TILED		fourcc_mod_code(VIVANTE, 1)
485 
486 /*
487  * Vivante 64x64 super-tiling layout
488  *
489  * This is a tiled layout using 64x64 pixel super-tiles, where each super-tile
490  * contains 8x4 groups of 2x4 tiles of 4x4 pixels (like above) each, all in row-
491  * major layout.
492  *
493  * For more information: see
494  * https://github.com/etnaviv/etna_viv/blob/master/doc/hardware.md#texture-tiling
495  */
496 #define DRM_FORMAT_MOD_VIVANTE_SUPER_TILED	fourcc_mod_code(VIVANTE, 2)
497 
498 /*
499  * Vivante 4x4 tiling layout for dual-pipe
500  *
501  * Same as the 4x4 tiling layout, except every second 4x4 pixel tile starts at a
502  * different base address. Offsets from the base addresses are therefore halved
503  * compared to the non-split tiled layout.
504  */
505 #define DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED	fourcc_mod_code(VIVANTE, 3)
506 
507 /*
508  * Vivante 64x64 super-tiling layout for dual-pipe
509  *
510  * Same as the 64x64 super-tiling layout, except every second 4x4 pixel tile
511  * starts at a different base address. Offsets from the base addresses are
512  * therefore halved compared to the non-split super-tiled layout.
513  */
514 #define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4)
515 
516 /* NVIDIA frame buffer modifiers */
517 
518 /*
519  * Tegra Tiled Layout, used by Tegra 2, 3 and 4.
520  *
521  * Pixels are arranged in simple tiles of 16 x 16 bytes.
522  */
523 #define DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED fourcc_mod_code(NVIDIA, 1)
524 
525 /*
526  * 16Bx2 Block Linear layout, used by desktop GPUs, and Tegra K1 and later
527  *
528  * Pixels are arranged in 64x8 Groups Of Bytes (GOBs). GOBs are then stacked
529  * vertically by a power of 2 (1 to 32 GOBs) to form a block.
530  *
531  * Within a GOB, data is ordered as 16B x 2 lines sectors laid in Z-shape.
532  *
533  * Parameter 'v' is the log2 encoding of the number of GOBs stacked vertically.
534  * Valid values are:
535  *
536  * 0 == ONE_GOB
537  * 1 == TWO_GOBS
538  * 2 == FOUR_GOBS
539  * 3 == EIGHT_GOBS
540  * 4 == SIXTEEN_GOBS
541  * 5 == THIRTYTWO_GOBS
542  *
543  * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format
544  * in full detail.
545  */
546 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(v) \
547 	fourcc_mod_code(NVIDIA, 0x10 | ((v) & 0xf))
548 
549 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_ONE_GOB \
550 	fourcc_mod_code(NVIDIA, 0x10)
551 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_TWO_GOB \
552 	fourcc_mod_code(NVIDIA, 0x11)
553 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_FOUR_GOB \
554 	fourcc_mod_code(NVIDIA, 0x12)
555 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_EIGHT_GOB \
556 	fourcc_mod_code(NVIDIA, 0x13)
557 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_SIXTEEN_GOB \
558 	fourcc_mod_code(NVIDIA, 0x14)
559 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_THIRTYTWO_GOB \
560 	fourcc_mod_code(NVIDIA, 0x15)
561 
562 /*
563  * Some Broadcom modifiers take parameters, for example the number of
564  * vertical lines in the image. Reserve the lower 32 bits for modifier
565  * type, and the next 24 bits for parameters. Top 8 bits are the
566  * vendor code.
567  */
568 #define __fourcc_mod_broadcom_param_shift 8
569 #define __fourcc_mod_broadcom_param_bits 48
570 #define fourcc_mod_broadcom_code(val, params) \
571 	fourcc_mod_code(BROADCOM, ((((__u64)params) << __fourcc_mod_broadcom_param_shift) | val))
572 #define fourcc_mod_broadcom_param(m) \
573 	((int)(((m) >> __fourcc_mod_broadcom_param_shift) &	\
574 	       ((1ULL << __fourcc_mod_broadcom_param_bits) - 1)))
575 #define fourcc_mod_broadcom_mod(m) \
576 	((m) & ~(((1ULL << __fourcc_mod_broadcom_param_bits) - 1) <<	\
577 		 __fourcc_mod_broadcom_param_shift))
578 
579 /*
580  * Broadcom VC4 "T" format
581  *
582  * This is the primary layout that the V3D GPU can texture from (it
583  * can't do linear).  The T format has:
584  *
585  * - 64b utiles of pixels in a raster-order grid according to cpp.  It's 4x4
586  *   pixels at 32 bit depth.
587  *
588  * - 1k subtiles made of a 4x4 raster-order grid of 64b utiles (so usually
589  *   16x16 pixels).
590  *
591  * - 4k tiles made of a 2x2 grid of 1k subtiles (so usually 32x32 pixels).  On
592  *   even 4k tile rows, they're arranged as (BL, TL, TR, BR), and on odd rows
593  *   they're (TR, BR, BL, TL), where bottom left is start of memory.
594  *
595  * - an image made of 4k tiles in rows either left-to-right (even rows of 4k
596  *   tiles) or right-to-left (odd rows of 4k tiles).
597  */
598 #define DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED fourcc_mod_code(BROADCOM, 1)
599 
600 /*
601  * Broadcom SAND format
602  *
603  * This is the native format that the H.264 codec block uses.  For VC4
604  * HVS, it is only valid for H.264 (NV12/21) and RGBA modes.
605  *
606  * The image can be considered to be split into columns, and the
607  * columns are placed consecutively into memory.  The width of those
608  * columns can be either 32, 64, 128, or 256 pixels, but in practice
609  * only 128 pixel columns are used.
610  *
611  * The pitch between the start of each column is set to optimally
612  * switch between SDRAM banks. This is passed as the number of lines
613  * of column width in the modifier (we can't use the stride value due
614  * to various core checks that look at it , so you should set the
615  * stride to width*cpp).
616  *
617  * Note that the column height for this format modifier is the same
618  * for all of the planes, assuming that each column contains both Y
619  * and UV.  Some SAND-using hardware stores UV in a separate tiled
620  * image from Y to reduce the column height, which is not supported
621  * with these modifiers.
622  */
623 
624 #define DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(v) \
625 	fourcc_mod_broadcom_code(2, v)
626 #define DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(v) \
627 	fourcc_mod_broadcom_code(3, v)
628 #define DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(v) \
629 	fourcc_mod_broadcom_code(4, v)
630 #define DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(v) \
631 	fourcc_mod_broadcom_code(5, v)
632 
633 #define DRM_FORMAT_MOD_BROADCOM_SAND32 \
634 	DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(0)
635 #define DRM_FORMAT_MOD_BROADCOM_SAND64 \
636 	DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(0)
637 #define DRM_FORMAT_MOD_BROADCOM_SAND128 \
638 	DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(0)
639 #define DRM_FORMAT_MOD_BROADCOM_SAND256 \
640 	DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(0)
641 
642 /* Broadcom UIF format
643  *
644  * This is the common format for the current Broadcom multimedia
645  * blocks, including V3D 3.x and newer, newer video codecs, and
646  * displays.
647  *
648  * The image consists of utiles (64b blocks), UIF blocks (2x2 utiles),
649  * and macroblocks (4x4 UIF blocks).  Those 4x4 UIF block groups are
650  * stored in columns, with padding between the columns to ensure that
651  * moving from one column to the next doesn't hit the same SDRAM page
652  * bank.
653  *
654  * To calculate the padding, it is assumed that each hardware block
655  * and the software driving it knows the platform's SDRAM page size,
656  * number of banks, and XOR address, and that it's identical between
657  * all blocks using the format.  This tiling modifier will use XOR as
658  * necessary to reduce the padding.  If a hardware block can't do XOR,
659  * the assumption is that a no-XOR tiling modifier will be created.
660  */
661 #define DRM_FORMAT_MOD_BROADCOM_UIF fourcc_mod_code(BROADCOM, 6)
662 
663 /*
664  * Arm Framebuffer Compression (AFBC) modifiers
665  *
666  * AFBC is a proprietary lossless image compression protocol and format.
667  * It provides fine-grained random access and minimizes the amount of data
668  * transferred between IP blocks.
669  *
670  * AFBC has several features which may be supported and/or used, which are
671  * represented using bits in the modifier. Not all combinations are valid,
672  * and different devices or use-cases may support different combinations.
673  *
674  * Further information on the use of AFBC modifiers can be found in
675  * Documentation/gpu/afbc.rst
676  */
677 
678 /*
679  * The top 4 bits (out of the 56 bits alloted for specifying vendor specific
680  * modifiers) denote the category for modifiers. Currently we have only two
681  * categories of modifiers ie AFBC and MISC. We can have a maximum of sixteen
682  * different categories.
683  */
684 #define DRM_FORMAT_MOD_ARM_CODE(__type, __val) \
685 	fourcc_mod_code(ARM, ((__u64)(__type) << 52) | ((__val) & 0x000fffffffffffffULL))
686 
687 #define DRM_FORMAT_MOD_ARM_TYPE_AFBC 0x00
688 #define DRM_FORMAT_MOD_ARM_TYPE_MISC 0x01
689 
690 #define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode) \
691 	DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_AFBC, __afbc_mode)
692 
693 /*
694  * AFBC superblock size
695  *
696  * Indicates the superblock size(s) used for the AFBC buffer. The buffer
697  * size (in pixels) must be aligned to a multiple of the superblock size.
698  * Four lowest significant bits(LSBs) are reserved for block size.
699  *
700  * Where one superblock size is specified, it applies to all planes of the
701  * buffer (e.g. 16x16, 32x8). When multiple superblock sizes are specified,
702  * the first applies to the Luma plane and the second applies to the Chroma
703  * plane(s). e.g. (32x8_64x4 means 32x8 Luma, with 64x4 Chroma).
704  * Multiple superblock sizes are only valid for multi-plane YCbCr formats.
705  */
706 #define AFBC_FORMAT_MOD_BLOCK_SIZE_MASK      0xf
707 #define AFBC_FORMAT_MOD_BLOCK_SIZE_16x16     (1ULL)
708 #define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8      (2ULL)
709 #define AFBC_FORMAT_MOD_BLOCK_SIZE_64x4      (3ULL)
710 #define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8_64x4 (4ULL)
711 
712 /*
713  * AFBC lossless colorspace transform
714  *
715  * Indicates that the buffer makes use of the AFBC lossless colorspace
716  * transform.
717  */
718 #define AFBC_FORMAT_MOD_YTR     (1ULL <<  4)
719 
720 /*
721  * AFBC block-split
722  *
723  * Indicates that the payload of each superblock is split. The second
724  * half of the payload is positioned at a predefined offset from the start
725  * of the superblock payload.
726  */
727 #define AFBC_FORMAT_MOD_SPLIT   (1ULL <<  5)
728 
729 /*
730  * AFBC sparse layout
731  *
732  * This flag indicates that the payload of each superblock must be stored at a
733  * predefined position relative to the other superblocks in the same AFBC
734  * buffer. This order is the same order used by the header buffer. In this mode
735  * each superblock is given the same amount of space as an uncompressed
736  * superblock of the particular format would require, rounding up to the next
737  * multiple of 128 bytes in size.
738  */
739 #define AFBC_FORMAT_MOD_SPARSE  (1ULL <<  6)
740 
741 /*
742  * AFBC copy-block restrict
743  *
744  * Buffers with this flag must obey the copy-block restriction. The restriction
745  * is such that there are no copy-blocks referring across the border of 8x8
746  * blocks. For the subsampled data the 8x8 limitation is also subsampled.
747  */
748 #define AFBC_FORMAT_MOD_CBR     (1ULL <<  7)
749 
750 /*
751  * AFBC tiled layout
752  *
753  * The tiled layout groups superblocks in 8x8 or 4x4 tiles, where all
754  * superblocks inside a tile are stored together in memory. 8x8 tiles are used
755  * for pixel formats up to and including 32 bpp while 4x4 tiles are used for
756  * larger bpp formats. The order between the tiles is scan line.
757  * When the tiled layout is used, the buffer size (in pixels) must be aligned
758  * to the tile size.
759  */
760 #define AFBC_FORMAT_MOD_TILED   (1ULL <<  8)
761 
762 /*
763  * AFBC solid color blocks
764  *
765  * Indicates that the buffer makes use of solid-color blocks, whereby bandwidth
766  * can be reduced if a whole superblock is a single color.
767  */
768 #define AFBC_FORMAT_MOD_SC      (1ULL <<  9)
769 
770 /*
771  * AFBC double-buffer
772  *
773  * Indicates that the buffer is allocated in a layout safe for front-buffer
774  * rendering.
775  */
776 #define AFBC_FORMAT_MOD_DB      (1ULL << 10)
777 
778 /*
779  * AFBC buffer content hints
780  *
781  * Indicates that the buffer includes per-superblock content hints.
782  */
783 #define AFBC_FORMAT_MOD_BCH     (1ULL << 11)
784 
785 /*
786  * Arm 16x16 Block U-Interleaved modifier
787  *
788  * This is used by Arm Mali Utgard and Midgard GPUs. It divides the image
789  * into 16x16 pixel blocks. Blocks are stored linearly in order, but pixels
790  * in the block are reordered.
791  */
792 #define DRM_FORMAT_MOD_ARM_16X16_BLOCK_U_INTERLEAVED \
793 	DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_MISC, 1ULL)
794 
795 /*
796  * Allwinner tiled modifier
797  *
798  * This tiling mode is implemented by the VPU found on all Allwinner platforms,
799  * codenamed sunxi. It is associated with a YUV format that uses either 2 or 3
800  * planes.
801  *
802  * With this tiling, the luminance samples are disposed in tiles representing
803  * 32x32 pixels and the chrominance samples in tiles representing 32x64 pixels.
804  * The pixel order in each tile is linear and the tiles are disposed linearly,
805  * both in row-major order.
806  */
807 #define DRM_FORMAT_MOD_ALLWINNER_TILED fourcc_mod_code(ALLWINNER, 1)
808 
809 #if defined(__cplusplus)
810 }
811 #endif
812 
813 #endif /* DRM_FOURCC_H */
814