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Searched refs:DefaultMode (Results 1 – 12 of 12) sorted by relevance

/netbsd/external/apache2/llvm/dist/llvm/utils/TableGen/
H A DInfoByHwMode.h36 DefaultMode = CodeGenHwModes::DefaultMode, enumerator
51 if (M != DefaultMode) in union_modes()
56 Modes.push_back(DefaultMode); in union_modes()
83 bool hasDefault() const { return hasMode(DefaultMode); } in hasDefault()
87 assert(hasMode(DefaultMode)); in get()
88 Map.insert({Mode, Map.at(DefaultMode)}); in get()
94 if (Mode != DefaultMode && F == Map.end()) in get()
95 F = Map.find(DefaultMode); in get()
102 return Map.size() == 1 && Map.begin()->first == DefaultMode; in isSimple()
113 Map.insert(std::make_pair(DefaultMode, I)); in makeSimple()
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H A DRegisterBankEmitter.cpp85 else if (RCWithLargestRegsSize->RSI.get(DefaultMode).SpillSize < in addRegisterClass()
86 RC->RSI.get(DefaultMode).SpillSize) in addRegisterClass()
247 unsigned Size = RC.RSI.get(DefaultMode).SpillSize; in emitBaseClassImplementation()
H A DInfoByHwMode.cpp27 if (Mode == DefaultMode) in getModeName()
69 auto D = Map.find(DefaultMode); in getOrCreateTypeForMode()
H A DCodeGenHwModes.h43 enum : unsigned { DefaultMode = 0 }; enumerator
H A DCodeGenHwModes.cpp81 return DefaultMode; in getHwModeId()
H A DCodeGenDAGPatterns.cpp118 if (DefaultMode == M) { in insert()
140 if (M == DefaultMode || hasMode(M)) in constrain()
142 Map.insert({M, Map.at(DefaultMode)}); in constrain()
777 const TypeSetByHwMode::SetType &LegalTypes = Legal.get(DefaultMode); in expandOverloads()
840 TypeSetByHwMode::SetType &LegalTypes = LegalCache.getOrCreate(DefaultMode); in getLegalTypes()
1761 if (S.get(DefaultMode).empty()) in setDefaultMode()
4371 if (M == DefaultMode) in ExpandHwModeBasedTypes()
4386 bool HasDefault = Modes.count(DefaultMode); in ExpandHwModeBasedTypes()
4388 AppendPattern(P, DefaultMode, DefaultCheck); in ExpandHwModeBasedTypes()
H A DCodeGenDAGPatterns.h224 return Map.size() == 1 && Map.begin()->first == DefaultMode; in isDefaultOnly()
H A DCodeGenRegisters.cpp795 RSI.insertRegSizeForMode(DefaultMode, RI); in CodeGenRegisterClass()
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonRegisterInfo.td321 def VecI1: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
323 def VecI8: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
325 def VecI16: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
327 def VecI32: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
330 def VecPI8: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
332 def VecPI16: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
334 def VecPI32: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
337 def VecQ8: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
339 def VecQ16: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
341 def VecQ32: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DSIModeRegister.cpp121 unsigned DefaultMode = FP_ROUND_ROUND_TO_NEAREST; member in __anonf4dcff7a0111::SIModeRegister
123 Status(FP_ROUND_MODE_DP(0x3), FP_ROUND_MODE_DP(DefaultMode));
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
H A DRISCV.td201 defvar RV32 = DefaultMode;
/netbsd/external/apache2/llvm/dist/llvm/include/llvm/Target/
H A DTarget.td34 def DefaultMode : HwMode<"">;