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Searched refs:EndGroup (Results 1 – 16 of 16) sorted by relevance

/netbsd/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
H A DSystemZHazardRecognizer.cpp51 assert((SC->NumMicroOps != 2 || (SC->BeginGroup && !SC->EndGroup)) && in getNumDecoderSlots()
53 assert((SC->NumMicroOps < 3 || (SC->BeginGroup && SC->EndGroup)) && in getNumDecoderSlots()
196 if (SC->BeginGroup && SC->EndGroup) in dumpSU()
200 else if (SC->EndGroup) in dumpSU()
336 if (CurrGroupSize >= GroupLim || SC->EndGroup) in EmitInstruction()
355 if (SC->EndGroup) { in groupingCost()
H A DSystemZScheduleZ196.td39 def : WriteRes<EndGroup, []> { let EndGroup = 1; }
44 let EndGroup = 1;
49 let EndGroup = 1;
54 let EndGroup = 1;
95 let EndGroup = 1; }
154 def : InstRW<[WLat1, LSU, EndGroup], (instregex "Return$")>;
204 def : InstRW<[WLat2LSU, RegReadAdv, FXU, LSU, EndGroup],
650 def : InstRW<[WLat3, FXU, EndGroup], (instregex "IPM$")>;
653 def : InstRW<[WLat3, LSU, EndGroup], (instregex "SPM$")>;
1096 def : InstRW<[WLat1, LSU, EndGroup], (instregex "SPKA$")>;
[all …]
H A DSystemZScheduleZEC12.td39 def : WriteRes<EndGroup, []> { let EndGroup = 1; }
44 let EndGroup = 1;
49 let EndGroup = 1;
54 let EndGroup = 1;
98 let EndGroup = 1; }
124 def : InstRW<[WLat1, FXU, EndGroup], (instregex "BRCT(G)?$")>;
159 def : InstRW<[WLat1, LSU, EndGroup], (instregex "Return$")>;
663 def : InstRW<[WLat3, FXU, EndGroup], (instregex "IPM$")>;
666 def : InstRW<[WLat3, LSU, EndGroup], (instregex "SPM$")>;
1140 def : InstRW<[WLat1, LSU, EndGroup], (instregex "SPKA$")>;
[all …]
H A DSystemZScheduleZ13.td39 def : WriteRes<EndGroup, []> { let EndGroup = 1; }
48 let EndGroup = 1;
53 let EndGroup = 1;
58 let EndGroup = 1;
114 let EndGroup = 1; }
140 def : InstRW<[WLat1, FXa, EndGroup], (instregex "BRCT(G)?$")>;
175 def : InstRW<[WLat1, FXb, EndGroup], (instregex "Return$")>;
586 def : InstRW<[FXb, EndGroup], (instregex "BPRP$")>;
693 def : InstRW<[WLat3, FXa, EndGroup], (instregex "IPM$")>;
696 def : InstRW<[WLat3, LSU, EndGroup], (instregex "SPM$")>;
[all …]
H A DSystemZScheduleZ14.td39 def : WriteRes<EndGroup, []> { let EndGroup = 1; }
48 let EndGroup = 1;
53 let EndGroup = 1;
58 let EndGroup = 1;
114 let EndGroup = 1; }
141 def : InstRW<[WLat1, FXa, EndGroup], (instregex "BRCT(G)?$")>;
176 def : InstRW<[WLat1, FXb, EndGroup], (instregex "Return$")>;
596 def : InstRW<[FXb, EndGroup], (instregex "BPRP$")>;
713 def : InstRW<[WLat3, FXa, EndGroup], (instregex "IPM$")>;
716 def : InstRW<[WLat3, LSU, EndGroup], (instregex "SPM$")>;
[all …]
H A DSystemZScheduleZ15.td39 def : WriteRes<EndGroup, []> { let EndGroup = 1; }
48 let EndGroup = 1;
53 let EndGroup = 1;
58 let EndGroup = 1;
114 let EndGroup = 1; }
141 def : InstRW<[WLat1, FXa, EndGroup], (instregex "BRCT(G)?$")>;
176 def : InstRW<[WLat1, FXb, EndGroup], (instregex "Return$")>;
610 def : InstRW<[FXb, EndGroup], (instregex "BPRP$")>;
728 def : InstRW<[WLat3, FXa, EndGroup], (instregex "IPM$")>;
731 def : InstRW<[WLat3, LSU, EndGroup], (instregex "SPM$")>;
[all …]
H A DSystemZSchedule.td20 def EndGroup : SchedWrite;
H A DSystemZMachineScheduler.cpp256 bool AffectsGrouping = (SC->isValid() && (SC->BeginGroup || SC->EndGroup)); in releaseTopNode()
/netbsd/external/apache2/llvm/dist/llvm/lib/MCA/Stages/
H A DInOrderIssueStage.cpp263 Bandwidth = Desc.EndGroup ? 0 : Bandwidth - NumMicroOps; in tryIssue()
323 if (CarriedOver.getInstruction()->getDesc().EndGroup) in updateCarriedOver()
H A DDispatchStage.cpp94 if (Desc.EndGroup) in dispatch()
/netbsd/external/apache2/llvm/dist/llvm/include/llvm/MC/
H A DMCSchedule.h119 uint16_t EndGroup : 1; member
/netbsd/external/apache2/llvm/dist/llvm/lib/MCA/
H A DInstrBuilder.cpp572 ID->EndGroup = SCDesc.EndGroup; in createInstrDescImpl()
/netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DTargetSchedule.cpp102 return SC->EndGroup; in mustEndGroup()
/netbsd/external/apache2/llvm/dist/llvm/utils/TableGen/
H A DSubtargetEmitter.cpp995 SCDesc.EndGroup = false; in GenSchedClassTables()
1096 SCDesc.EndGroup |= WriteRes->getValueAsBit("EndGroup"); in GenSchedClassTables()
1098 SCDesc.EndGroup |= WriteRes->getValueAsBit("SingleIssue"); in GenSchedClassTables()
1319 << ", " << ( MCDesc.EndGroup ? "true" : "false" ) in EmitSchedClassTables()
/netbsd/external/apache2/llvm/dist/llvm/include/llvm/MCA/
H A DInstruction.h377 bool EndGroup; member
/netbsd/external/apache2/llvm/dist/llvm/include/llvm/Target/
H A DTargetSchedule.td256 bit EndGroup = false;