| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86TargetTransformInfo.cpp | 2482 { ISD::FMAXNUM, MVT::f32, 2 }, in getTypeBasedIntrinsicInstrCost()
2483 { ISD::FMAXNUM, MVT::v4f32, 2 }, in getTypeBasedIntrinsicInstrCost()
2484 { ISD::FMAXNUM, MVT::v8f32, 2 }, in getTypeBasedIntrinsicInstrCost()
2485 { ISD::FMAXNUM, MVT::v16f32, 2 }, in getTypeBasedIntrinsicInstrCost()
2486 { ISD::FMAXNUM, MVT::f64, 2 }, in getTypeBasedIntrinsicInstrCost()
2487 { ISD::FMAXNUM, MVT::v2f64, 2 }, in getTypeBasedIntrinsicInstrCost()
2488 { ISD::FMAXNUM, MVT::v4f64, 2 }, in getTypeBasedIntrinsicInstrCost()
2489 { ISD::FMAXNUM, MVT::v8f64, 2 }, in getTypeBasedIntrinsicInstrCost()
2710 { ISD::FMAXNUM, MVT::f64, 4 }, in getTypeBasedIntrinsicInstrCost()
2711 { ISD::FMAXNUM, MVT::v2f64, 4 }, in getTypeBasedIntrinsicInstrCost()
[all …]
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| /netbsd/external/apache2/llvm/dist/llvm/include/llvm/IR/ |
| H A D | ConstrainedOps.def | 85 DAG_FUNCTION(maxnum, 2, 0, experimental_constrained_maxnum, FMAXNUM)
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| /netbsd/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 889 FMAXNUM, enumerator
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| H A D | BasicTTIImpl.h | 1559 ISDs.push_back(ISD::FMAXNUM); in getTypeBasedIntrinsicInstrCost()
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| H A D | TargetLowering.h | 2441 case ISD::FMAXNUM: in isCommutativeBinOp()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCTargetTransformInfo.cpp | 507 case Intrinsic::maxnum: Opcode = ISD::FMAXNUM; break; in mightUseCTR()
624 Opcode = ISD::FMAXNUM; break; in mightUseCTR()
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| /netbsd/external/apache2/llvm/dist/llvm/docs/GlobalISel/ |
| H A D | GenericOpcode.rst | 493 The return value of (FMAXNUM 0.0, -0.0) could be either 0.0 or -0.0.
506 definition. This differs from FMAXNUM in the handling of signaling NaNs. If one
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 459 setOperationAction(ISD::FMAXNUM, MVT::f32, Custom); in SITargetLowering()
461 setOperationAction(ISD::FMAXNUM, MVT::f64, Custom); in SITargetLowering()
652 setOperationAction(ISD::FMAXNUM, MVT::f16, Custom); in SITargetLowering()
804 setTargetDAGCombine(ISD::FMAXNUM); in SITargetLowering()
4526 case ISD::FMAXNUM: in LowerOperation()
6462 return DAG.getNode(ISD::FMAXNUM, DL, VT, Tmp, in LowerINTRINSIC_WO_CHAIN()
9381 case ISD::FMAXNUM: in fp16SrcZerosHighBits()
9568 case ISD::FMAXNUM: in isCanonicalized()
9825 case ISD::FMAXNUM: in minMaxOpcToMin3Max3Opc()
10171 case ISD::FMAXNUM: in performExtractVectorEltCombine()
[all …]
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| H A D | AMDGPUISelLowering.cpp | 302 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal); in AMDGPUTargetLowering()
463 setOperationAction(ISD::FMAXNUM, VT, Expand); in AMDGPUTargetLowering()
592 case ISD::FMAXNUM: in fnegFoldsIntoOp()
3628 case ISD::FMAXNUM: in inverseMinMax()
3631 return ISD::FMAXNUM; in inverseMinMax()
3746 case ISD::FMAXNUM: in performFNegCombine()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorOps.cpp | 409 case ISD::FMAXNUM: in LegalizeOp()
819 case ISD::FMAXNUM: in Expand()
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| H A D | SelectionDAGDumper.cpp | 186 case ISD::FMAXNUM: return "fmaxnum"; in getOperationName()
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| H A D | LegalizeFloatTypes.cpp | 71 case ISD::FMAXNUM: R = SoftenFloatRes_FMAXNUM(N); break; in SoftenFloatResult()
1190 case ISD::FMAXNUM: ExpandFloatRes_FMAXNUM(N, Lo, Hi); break; in ExpandFloatResult()
2251 case ISD::FMAXNUM: in PromoteFloatResult()
2616 case ISD::FMAXNUM: in SoftPromoteHalfResult()
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| H A D | SelectionDAGBuilder.cpp | 3311 case SPNB_RETURNS_OTHER: Opc = ISD::FMAXNUM; break; in visitSelect()
3314 if (TLI.isOperationLegalOrCustom(ISD::FMAXNUM, VT)) in visitSelect()
3315 Opc = ISD::FMAXNUM; in visitSelect()
3319 Opc = TLI.isOperationLegalOrCustom(ISD::FMAXNUM, VT.getScalarType()) ? in visitSelect()
3320 ISD::FMAXNUM : ISD::FMAXIMUM; in visitSelect()
6263 setValue(&I, DAG.getNode(ISD::FMAXNUM, sdl, in visitIntrinsicCall()
7916 if (visitBinaryFloatCall(I, ISD::FMAXNUM)) in visitCall()
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| H A D | LegalizeDAG.cpp | 3149 case ISD::FMAXNUM: { in ExpandNode()
3944 case ISD::FMAXNUM: in ConvertNodeToLibcall()
4678 case ISD::FMAXNUM: in PromoteNode()
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| H A D | LegalizeVectorTypes.cpp | 118 case ISD::FMAXNUM: in ScalarizeVectorResult()
1018 case ISD::FMAXNUM: in SplitVectorResult()
3019 case ISD::FMAXNUM: in WidenVectorResult()
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| H A D | SelectionDAG.cpp | 397 return ISD::FMAXNUM; in getVecReduceBaseOpcode()
4346 case ISD::FMAXNUM: { in isKnownNeverNaN()
10521 case ISD::FMAXNUM: { in getNeutralElement()
10527 if (Opcode == ISD::FMAXNUM) in getNeutralElement()
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| /netbsd/external/apache2/llvm/dist/llvm/include/llvm/Target/ |
| H A D | GenericOpcodes.td | 736 // FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two
759 // FMINNUM/FMAXNUM in the handling of signaling NaNs. If one input is a
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| H A D | TargetSelectionDAG.td | 464 def fmaxnum : SDNode<"ISD::FMAXNUM" , SDTFPBinOp,
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1642 ISD::FMINNUM, ISD::FMAXNUM, ISD::FSINCOS, in HexagonTargetLowering()
1762 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal); in HexagonTargetLowering()
1799 setOperationAction(ISD::FMAXNUM, MVT::f64, Legal); in HexagonTargetLowering()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 312 setOperationAction(ISD::FMAXNUM, MVT::f16, Legal); in RISCVTargetLowering()
324 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal); in RISCVTargetLowering()
341 setOperationAction(ISD::FMAXNUM, MVT::f64, Legal); in RISCVTargetLowering()
568 setOperationAction(ISD::FMAXNUM, VT, Legal); in RISCVTargetLowering()
769 setOperationAction(ISD::FMAXNUM, VT, Custom); in RISCVTargetLowering()
2398 case ISD::FMAXNUM: in LowerOperation()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 552 setOperationAction(ISD::FMAXNUM, MVT::f64, Legal); in SystemZTargetLowering()
557 setOperationAction(ISD::FMAXNUM, MVT::v2f64, Legal); in SystemZTargetLowering()
562 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal); in SystemZTargetLowering()
567 setOperationAction(ISD::FMAXNUM, MVT::v4f32, Legal); in SystemZTargetLowering()
572 setOperationAction(ISD::FMAXNUM, MVT::f128, Legal); in SystemZTargetLowering()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 743 setOperationAction(ISD::FMAXNUM, VT, Expand); in initActions()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 557 ISD::FABS, ISD::FMINNUM, ISD::FMAXNUM}) { in NVPTXTargetLowering()
564 setOperationAction(ISD::FMAXNUM, MVT::f16, Promote); in NVPTXTargetLowering()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 355 setOperationAction(ISD::FMAXNUM, VT, Legal); in addMVEVectorTypes()
756 setOperationAction(ISD::FMAXNUM, MVT::f16, Legal); in ARMTargetLowering()
1444 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal); in ARMTargetLowering()
1447 setOperationAction(ISD::FMAXNUM, MVT::v2f32, Legal); in ARMTargetLowering()
1449 setOperationAction(ISD::FMAXNUM, MVT::v4f32, Legal); in ARMTargetLowering()
1460 setOperationAction(ISD::FMAXNUM, MVT::f64, Legal); in ARMTargetLowering()
1500 setOperationAction(ISD::FMAXNUM, MVT::v4f16, Legal); in ARMTargetLowering()
1502 setOperationAction(ISD::FMAXNUM, MVT::v8f16, Legal); in ARMTargetLowering()
3966 ? ISD::FMINNUM : ISD::FMAXNUM; in LowerINTRINSIC_WO_CHAIN()
9661 case ISD::VECREDUCE_FMAX: BaseOpcode = ISD::FMAXNUM; break; in LowerVecReduce()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 628 setOperationAction(ISD::FMAXNUM, MVT::f16, Promote); in AArch64TargetLowering()
692 setOperationAction(ISD::FMAXNUM, Ty, Legal); in AArch64TargetLowering()
710 setOperationAction(ISD::FMAXNUM, MVT::f16, Legal); in AArch64TargetLowering()
1227 setOperationAction(ISD::FMAXNUM, VT, Custom); in AArch64TargetLowering()
1421 {ISD::FMINIMUM, ISD::FMAXIMUM, ISD::FMINNUM, ISD::FMAXNUM}) in addTypeForNEON()
1476 setOperationAction(ISD::FMAXNUM, VT, Custom); in addTypeForFixedLengthSVE()
4691 case ISD::FMAXNUM: in LowerOperation()
13947 return DAG.getNode(ISD::FMAXNUM, SDLoc(N), N->getValueType(0), in performIntrinsicCombine()
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