1 /* $NetBSD: dwc2_hw.h,v 1.4 2016/02/14 10:53:30 skrll Exp $ */ 2 3 /* 4 * hw.h - DesignWare HS OTG Controller hardware definitions 5 * 6 * Copyright 2004-2013 Synopsys, Inc. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions, and the following disclaimer, 13 * without modification. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The names of the above-listed copyright holders may not be used 18 * to endorse or promote products derived from this software without 19 * specific prior written permission. 20 * 21 * ALTERNATIVELY, this software may be distributed under the terms of the 22 * GNU General Public License ("GPL") as published by the Free Software 23 * Foundation; either version 2 of the License, or (at your option) any 24 * later version. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #ifndef __DWC2_HW_H__ 40 #define __DWC2_HW_H__ 41 42 #define HSOTG_REG(x) (x) 43 44 #define GOTGCTL HSOTG_REG(0x000) 45 #define GOTGCTL_CHIRPEN (1 << 27) 46 #define GOTGCTL_MULT_VALID_BC_MASK (0x1f << 22) 47 #define GOTGCTL_MULT_VALID_BC_SHIFT 22 48 #define GOTGCTL_OTGVER (1 << 20) 49 #define GOTGCTL_BSESVLD (1 << 19) 50 #define GOTGCTL_ASESVLD (1 << 18) 51 #define GOTGCTL_DBNC_SHORT (1 << 17) 52 #define GOTGCTL_CONID_B (1 << 16) 53 #define GOTGCTL_DEVHNPEN (1 << 11) 54 #define GOTGCTL_HSTSETHNPEN (1 << 10) 55 #define GOTGCTL_HNPREQ (1 << 9) 56 #define GOTGCTL_HSTNEGSCS (1 << 8) 57 #define GOTGCTL_SESREQ (1 << 1) 58 #define GOTGCTL_SESREQSCS (1 << 0) 59 60 #define GOTGINT HSOTG_REG(0x004) 61 #define GOTGINT_DBNCE_DONE (1 << 19) 62 #define GOTGINT_A_DEV_TOUT_CHG (1 << 18) 63 #define GOTGINT_HST_NEG_DET (1 << 17) 64 #define GOTGINT_HST_NEG_SUC_STS_CHNG (1 << 9) 65 #define GOTGINT_SES_REQ_SUC_STS_CHNG (1 << 8) 66 #define GOTGINT_SES_END_DET (1 << 2) 67 68 #define GAHBCFG HSOTG_REG(0x008) 69 #define GAHBCFG_AHB_SINGLE (1 << 23) 70 #define GAHBCFG_NOTI_ALL_DMA_WRIT (1 << 22) 71 #define GAHBCFG_REM_MEM_SUPP (1 << 21) 72 #define GAHBCFG_P_TXF_EMP_LVL (1 << 8) 73 #define GAHBCFG_NP_TXF_EMP_LVL (1 << 7) 74 #define GAHBCFG_DMA_EN (1 << 5) 75 #define GAHBCFG_HBSTLEN_MASK (0xf << 1) 76 #define GAHBCFG_HBSTLEN_SHIFT 1 77 #define GAHBCFG_HBSTLEN_SINGLE 0 78 #define GAHBCFG_HBSTLEN_INCR 1 79 #define GAHBCFG_HBSTLEN_INCR4 3 80 #define GAHBCFG_HBSTLEN_INCR8 5 81 #define GAHBCFG_HBSTLEN_INCR16 7 82 #define GAHBCFG_GLBL_INTR_EN (1 << 0) 83 #define GAHBCFG_CTRL_MASK (GAHBCFG_P_TXF_EMP_LVL | \ 84 GAHBCFG_NP_TXF_EMP_LVL | \ 85 GAHBCFG_DMA_EN | \ 86 GAHBCFG_GLBL_INTR_EN) 87 88 #define GUSBCFG HSOTG_REG(0x00C) 89 #define GUSBCFG_FORCEDEVMODE (1 << 30) 90 #define GUSBCFG_FORCEHOSTMODE (1 << 29) 91 #define GUSBCFG_TXENDDELAY (1 << 28) 92 #define GUSBCFG_ICTRAFFICPULLREMOVE (1 << 27) 93 #define GUSBCFG_ICUSBCAP (1 << 26) 94 #define GUSBCFG_ULPI_INT_PROT_DIS (1 << 25) 95 #define GUSBCFG_INDICATORPASSTHROUGH (1 << 24) 96 #define GUSBCFG_INDICATORCOMPLEMENT (1 << 23) 97 #define GUSBCFG_TERMSELDLPULSE (1 << 22) 98 #define GUSBCFG_ULPI_INT_VBUS_IND (1 << 21) 99 #define GUSBCFG_ULPI_EXT_VBUS_DRV (1 << 20) 100 #define GUSBCFG_ULPI_CLK_SUSP_M (1 << 19) 101 #define GUSBCFG_ULPI_AUTO_RES (1 << 18) 102 #define GUSBCFG_ULPI_FS_LS (1 << 17) 103 #define GUSBCFG_OTG_UTMI_FS_SEL (1 << 16) 104 #define GUSBCFG_PHY_LP_CLK_SEL (1 << 15) 105 #define GUSBCFG_USBTRDTIM_MASK (0xf << 10) 106 #define GUSBCFG_USBTRDTIM_SHIFT 10 107 #define GUSBCFG_HNPCAP (1 << 9) 108 #define GUSBCFG_SRPCAP (1 << 8) 109 #define GUSBCFG_DDRSEL (1 << 7) 110 #define GUSBCFG_PHYSEL (1 << 6) 111 #define GUSBCFG_FSINTF (1 << 5) 112 #define GUSBCFG_ULPI_UTMI_SEL (1 << 4) 113 #define GUSBCFG_PHYIF16 (1 << 3) 114 #define GUSBCFG_PHYIF8 (0 << 3) 115 #define GUSBCFG_TOUTCAL_MASK (0x7 << 0) 116 #define GUSBCFG_TOUTCAL_SHIFT 0 117 #define GUSBCFG_TOUTCAL_LIMIT 0x7 118 #define GUSBCFG_TOUTCAL(_x) ((_x) << 0) 119 120 #define GRSTCTL HSOTG_REG(0x010) 121 #define GRSTCTL_AHBIDLE (1 << 31) 122 #define GRSTCTL_DMAREQ (1 << 30) 123 #define GRSTCTL_TXFNUM_MASK (0x1f << 6) 124 #define GRSTCTL_TXFNUM_SHIFT 6 125 #define GRSTCTL_TXFNUM_LIMIT 0x1f 126 #define GRSTCTL_TXFNUM(_x) ((_x) << 6) 127 #define GRSTCTL_TXFFLSH (1 << 5) 128 #define GRSTCTL_RXFFLSH (1 << 4) 129 #define GRSTCTL_IN_TKNQ_FLSH (1 << 3) 130 #define GRSTCTL_FRMCNTRRST (1 << 2) 131 #define GRSTCTL_HSFTRST (1 << 1) 132 #define GRSTCTL_CSFTRST (1 << 0) 133 134 #define GINTSTS HSOTG_REG(0x014) 135 #define GINTMSK HSOTG_REG(0x018) 136 #define GINTSTS_WKUPINT (1 << 31) 137 #define GINTSTS_SESSREQINT (1 << 30) 138 #define GINTSTS_DISCONNINT (1 << 29) 139 #define GINTSTS_CONIDSTSCHNG (1 << 28) 140 #define GINTSTS_LPMTRANRCVD (1 << 27) 141 #define GINTSTS_PTXFEMP (1 << 26) 142 #define GINTSTS_HCHINT (1 << 25) 143 #define GINTSTS_PRTINT (1 << 24) 144 #define GINTSTS_RESETDET (1 << 23) 145 #define GINTSTS_FET_SUSP (1 << 22) 146 #define GINTSTS_INCOMPL_IP (1 << 21) 147 #define GINTSTS_INCOMPL_SOOUT (1 << 21) 148 #define GINTSTS_INCOMPL_SOIN (1 << 20) 149 #define GINTSTS_OEPINT (1 << 19) 150 #define GINTSTS_IEPINT (1 << 18) 151 #define GINTSTS_EPMIS (1 << 17) 152 #define GINTSTS_RESTOREDONE (1 << 16) 153 #define GINTSTS_EOPF (1 << 15) 154 #define GINTSTS_ISOUTDROP (1 << 14) 155 #define GINTSTS_ENUMDONE (1 << 13) 156 #define GINTSTS_USBRST (1 << 12) 157 #define GINTSTS_USBSUSP (1 << 11) 158 #define GINTSTS_ERLYSUSP (1 << 10) 159 #define GINTSTS_I2CINT (1 << 9) 160 #define GINTSTS_ULPI_CK_INT (1 << 8) 161 #define GINTSTS_GOUTNAKEFF (1 << 7) 162 #define GINTSTS_GINNAKEFF (1 << 6) 163 #define GINTSTS_NPTXFEMP (1 << 5) 164 #define GINTSTS_RXFLVL (1 << 4) 165 #define GINTSTS_SOF (1 << 3) 166 #define GINTSTS_OTGINT (1 << 2) 167 #define GINTSTS_MODEMIS (1 << 1) 168 #define GINTSTS_CURMODE_HOST (1 << 0) 169 170 #define GRXSTSR HSOTG_REG(0x01C) 171 #define GRXSTSP HSOTG_REG(0x020) 172 #define GRXSTS_FN_MASK (0x7f << 25) 173 #define GRXSTS_FN_SHIFT 25 174 #define GRXSTS_PKTSTS_MASK (0xf << 17) 175 #define GRXSTS_PKTSTS_SHIFT 17 176 #define GRXSTS_PKTSTS_GLOBALOUTNAK 1 177 #define GRXSTS_PKTSTS_OUTRX 2 178 #define GRXSTS_PKTSTS_HCHIN 2 179 #define GRXSTS_PKTSTS_OUTDONE 3 180 #define GRXSTS_PKTSTS_HCHIN_XFER_COMP 3 181 #define GRXSTS_PKTSTS_SETUPDONE 4 182 #define GRXSTS_PKTSTS_DATATOGGLEERR 5 183 #define GRXSTS_PKTSTS_SETUPRX 6 184 #define GRXSTS_PKTSTS_HCHHALTED 7 185 #define GRXSTS_HCHNUM_MASK (0xf << 0) 186 #define GRXSTS_HCHNUM_SHIFT 0 187 #define GRXSTS_DPID_MASK (0x3 << 15) 188 #define GRXSTS_DPID_SHIFT 15 189 #define GRXSTS_BYTECNT_MASK (0x7ff << 4) 190 #define GRXSTS_BYTECNT_SHIFT 4 191 #define GRXSTS_EPNUM_MASK (0xf << 0) 192 #define GRXSTS_EPNUM_SHIFT 0 193 194 #define GRXFSIZ HSOTG_REG(0x024) 195 #define GRXFSIZ_DEPTH_MASK (0xffff << 0) 196 #define GRXFSIZ_DEPTH_SHIFT 0 197 198 #define GNPTXFSIZ HSOTG_REG(0x028) 199 /* Use FIFOSIZE_* constants to access this register */ 200 201 #define GNPTXSTS HSOTG_REG(0x02C) 202 #define GNPTXSTS_NP_TXQ_TOP_MASK (0x7f << 24) 203 #define GNPTXSTS_NP_TXQ_TOP_SHIFT 24 204 #define GNPTXSTS_NP_TXQ_SPC_AVAIL_MASK (0xff << 16) 205 #define GNPTXSTS_NP_TXQ_SPC_AVAIL_SHIFT 16 206 #define GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(_v) (((_v) >> 16) & 0xff) 207 #define GNPTXSTS_NP_TXF_SPC_AVAIL_MASK (0xffff << 0) 208 #define GNPTXSTS_NP_TXF_SPC_AVAIL_SHIFT 0 209 #define GNPTXSTS_NP_TXF_SPC_AVAIL_GET(_v) (((_v) >> 0) & 0xffff) 210 211 #define GI2CCTL HSOTG_REG(0x0030) 212 #define GI2CCTL_BSYDNE (1 << 31) 213 #define GI2CCTL_RW (1 << 30) 214 #define GI2CCTL_I2CDATSE0 (1 << 28) 215 #define GI2CCTL_I2CDEVADDR_MASK (0x3 << 26) 216 #define GI2CCTL_I2CDEVADDR_SHIFT 26 217 #define GI2CCTL_I2CSUSPCTL (1 << 25) 218 #define GI2CCTL_ACK (1 << 24) 219 #define GI2CCTL_I2CEN (1 << 23) 220 #define GI2CCTL_ADDR_MASK (0x7f << 16) 221 #define GI2CCTL_ADDR_SHIFT 16 222 #define GI2CCTL_REGADDR_MASK (0xff << 8) 223 #define GI2CCTL_REGADDR_SHIFT 8 224 #define GI2CCTL_RWDATA_MASK (0xff << 0) 225 #define GI2CCTL_RWDATA_SHIFT 0 226 227 #define GPVNDCTL HSOTG_REG(0x0034) 228 #define GGPIO HSOTG_REG(0x0038) 229 #define GUID HSOTG_REG(0x003c) 230 #define GSNPSID HSOTG_REG(0x0040) 231 #define GHWCFG1 HSOTG_REG(0x0044) 232 233 #define GHWCFG2 HSOTG_REG(0x0048) 234 #define GHWCFG2_OTG_ENABLE_IC_USB (1 << 31) 235 #define GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK (0x1f << 26) 236 #define GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT 26 237 #define GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK (0x3 << 24) 238 #define GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT 24 239 #define GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK (0x3 << 22) 240 #define GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT 22 241 #define GHWCFG2_MULTI_PROC_INT (1 << 20) 242 #define GHWCFG2_DYNAMIC_FIFO (1 << 19) 243 #define GHWCFG2_PERIO_EP_SUPPORTED (1 << 18) 244 #define GHWCFG2_NUM_HOST_CHAN_MASK (0xf << 14) 245 #define GHWCFG2_NUM_HOST_CHAN_SHIFT 14 246 #define GHWCFG2_NUM_DEV_EP_MASK (0xf << 10) 247 #define GHWCFG2_NUM_DEV_EP_SHIFT 10 248 #define GHWCFG2_FS_PHY_TYPE_MASK (0x3 << 8) 249 #define GHWCFG2_FS_PHY_TYPE_SHIFT 8 250 #define GHWCFG2_FS_PHY_TYPE_NOT_SUPPORTED 0 251 #define GHWCFG2_FS_PHY_TYPE_DEDICATED 1 252 #define GHWCFG2_FS_PHY_TYPE_SHARED_UTMI 2 253 #define GHWCFG2_FS_PHY_TYPE_SHARED_ULPI 3 254 #define GHWCFG2_HS_PHY_TYPE_MASK (0x3 << 6) 255 #define GHWCFG2_HS_PHY_TYPE_SHIFT 6 256 #define GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED 0 257 #define GHWCFG2_HS_PHY_TYPE_UTMI 1 258 #define GHWCFG2_HS_PHY_TYPE_ULPI 2 259 #define GHWCFG2_HS_PHY_TYPE_UTMI_ULPI 3 260 #define GHWCFG2_POINT2POINT (1 << 5) 261 #define GHWCFG2_ARCHITECTURE_MASK (0x3 << 3) 262 #define GHWCFG2_ARCHITECTURE_SHIFT 3 263 #define GHWCFG2_SLAVE_ONLY_ARCH 0 264 #define GHWCFG2_EXT_DMA_ARCH 1 265 #define GHWCFG2_INT_DMA_ARCH 2 266 #define GHWCFG2_OP_MODE_MASK (0x7 << 0) 267 #define GHWCFG2_OP_MODE_SHIFT 0 268 #define GHWCFG2_OP_MODE_HNP_SRP_CAPABLE 0 269 #define GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE 1 270 #define GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE 2 271 #define GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE 3 272 #define GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE 4 273 #define GHWCFG2_OP_MODE_SRP_CAPABLE_HOST 5 274 #define GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST 6 275 #define GHWCFG2_OP_MODE_UNDEFINED 7 276 277 #define GHWCFG3 HSOTG_REG(0x004c) 278 #define GHWCFG3_DFIFO_DEPTH_MASK (0xffff << 16) 279 #define GHWCFG3_DFIFO_DEPTH_SHIFT 16 280 #define GHWCFG3_OTG_LPM_EN (1 << 15) 281 #define GHWCFG3_BC_SUPPORT (1 << 14) 282 #define GHWCFG3_OTG_ENABLE_HSIC (1 << 13) 283 #define GHWCFG3_ADP_SUPP (1 << 12) 284 #define GHWCFG3_SYNCH_RESET_TYPE (1 << 11) 285 #define GHWCFG3_OPTIONAL_FEATURES (1 << 10) 286 #define GHWCFG3_VENDOR_CTRL_IF (1 << 9) 287 #define GHWCFG3_I2C (1 << 8) 288 #define GHWCFG3_OTG_FUNC (1 << 7) 289 #define GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK (0x7 << 4) 290 #define GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT 4 291 #define GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK (0xf << 0) 292 #define GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT 0 293 294 #define GHWCFG4 HSOTG_REG(0x0050) 295 #define GHWCFG4_DESC_DMA_DYN (1 << 31) 296 #define GHWCFG4_DESC_DMA (1 << 30) 297 #define GHWCFG4_NUM_IN_EPS_MASK (0xf << 26) 298 #define GHWCFG4_NUM_IN_EPS_SHIFT 26 299 #define GHWCFG4_DED_FIFO_EN (1 << 25) 300 #define GHWCFG4_DED_FIFO_SHIFT 25 301 #define GHWCFG4_SESSION_END_FILT_EN (1 << 24) 302 #define GHWCFG4_B_VALID_FILT_EN (1 << 23) 303 #define GHWCFG4_A_VALID_FILT_EN (1 << 22) 304 #define GHWCFG4_VBUS_VALID_FILT_EN (1 << 21) 305 #define GHWCFG4_IDDIG_FILT_EN (1 << 20) 306 #define GHWCFG4_NUM_DEV_MODE_CTRL_EP_MASK (0xf << 16) 307 #define GHWCFG4_NUM_DEV_MODE_CTRL_EP_SHIFT 16 308 #define GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK (0x3 << 14) 309 #define GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT 14 310 #define GHWCFG4_UTMI_PHY_DATA_WIDTH_8 0 311 #define GHWCFG4_UTMI_PHY_DATA_WIDTH_16 1 312 #define GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16 2 313 #define GHWCFG4_XHIBER (1 << 7) 314 #define GHWCFG4_HIBER (1 << 6) 315 #define GHWCFG4_MIN_AHB_FREQ (1 << 5) 316 #define GHWCFG4_POWER_OPTIMIZ (1 << 4) 317 #define GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK (0xf << 0) 318 #define GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT 0 319 320 #define GLPMCFG HSOTG_REG(0x0054) 321 #define GLPMCFG_INV_SEL_HSIC (1 << 31) 322 #define GLPMCFG_HSIC_CONNECT (1 << 30) 323 #define GLPMCFG_RETRY_COUNT_STS_MASK (0x7 << 25) 324 #define GLPMCFG_RETRY_COUNT_STS_SHIFT 25 325 #define GLPMCFG_SEND_LPM (1 << 24) 326 #define GLPMCFG_RETRY_COUNT_MASK (0x7 << 21) 327 #define GLPMCFG_RETRY_COUNT_SHIFT 21 328 #define GLPMCFG_LPM_CHAN_INDEX_MASK (0xf << 17) 329 #define GLPMCFG_LPM_CHAN_INDEX_SHIFT 17 330 #define GLPMCFG_SLEEP_STATE_RESUMEOK (1 << 16) 331 #define GLPMCFG_PRT_SLEEP_STS (1 << 15) 332 #define GLPMCFG_LPM_RESP_MASK (0x3 << 13) 333 #define GLPMCFG_LPM_RESP_SHIFT 13 334 #define GLPMCFG_HIRD_THRES_MASK (0x1f << 8) 335 #define GLPMCFG_HIRD_THRES_SHIFT 8 336 #define GLPMCFG_HIRD_THRES_EN (0x10 << 8) 337 #define GLPMCFG_EN_UTMI_SLEEP (1 << 7) 338 #define GLPMCFG_REM_WKUP_EN (1 << 6) 339 #define GLPMCFG_HIRD_MASK (0xf << 2) 340 #define GLPMCFG_HIRD_SHIFT 2 341 #define GLPMCFG_APPL_RESP (1 << 1) 342 #define GLPMCFG_LPM_CAP_EN (1 << 0) 343 344 #define GPWRDN HSOTG_REG(0x0058) 345 #define GPWRDN_MULT_VAL_ID_BC_MASK (0x1f << 24) 346 #define GPWRDN_MULT_VAL_ID_BC_SHIFT 24 347 #define GPWRDN_ADP_INT (1 << 23) 348 #define GPWRDN_BSESSVLD (1 << 22) 349 #define GPWRDN_IDSTS (1 << 21) 350 #define GPWRDN_LINESTATE_MASK (0x3 << 19) 351 #define GPWRDN_LINESTATE_SHIFT 19 352 #define GPWRDN_STS_CHGINT_MSK (1 << 18) 353 #define GPWRDN_STS_CHGINT (1 << 17) 354 #define GPWRDN_SRP_DET_MSK (1 << 16) 355 #define GPWRDN_SRP_DET (1 << 15) 356 #define GPWRDN_CONNECT_DET_MSK (1 << 14) 357 #define GPWRDN_CONNECT_DET (1 << 13) 358 #define GPWRDN_DISCONN_DET_MSK (1 << 12) 359 #define GPWRDN_DISCONN_DET (1 << 11) 360 #define GPWRDN_RST_DET_MSK (1 << 10) 361 #define GPWRDN_RST_DET (1 << 9) 362 #define GPWRDN_LNSTSCHG_MSK (1 << 8) 363 #define GPWRDN_LNSTSCHG (1 << 7) 364 #define GPWRDN_DIS_VBUS (1 << 6) 365 #define GPWRDN_PWRDNSWTCH (1 << 5) 366 #define GPWRDN_PWRDNRSTN (1 << 4) 367 #define GPWRDN_PWRDNCLMP (1 << 3) 368 #define GPWRDN_RESTORE (1 << 2) 369 #define GPWRDN_PMUACTV (1 << 1) 370 #define GPWRDN_PMUINTSEL (1 << 0) 371 372 #define GDFIFOCFG HSOTG_REG(0x005c) 373 #define GDFIFOCFG_EPINFOBASE_MASK (0xffff << 16) 374 #define GDFIFOCFG_EPINFOBASE_SHIFT 16 375 #define GDFIFOCFG_GDFIFOCFG_MASK (0xffff << 0) 376 #define GDFIFOCFG_GDFIFOCFG_SHIFT 0 377 378 #define ADPCTL HSOTG_REG(0x0060) 379 #define ADPCTL_AR_MASK (0x3 << 27) 380 #define ADPCTL_AR_SHIFT 27 381 #define ADPCTL_ADP_TMOUT_INT_MSK (1 << 26) 382 #define ADPCTL_ADP_SNS_INT_MSK (1 << 25) 383 #define ADPCTL_ADP_PRB_INT_MSK (1 << 24) 384 #define ADPCTL_ADP_TMOUT_INT (1 << 23) 385 #define ADPCTL_ADP_SNS_INT (1 << 22) 386 #define ADPCTL_ADP_PRB_INT (1 << 21) 387 #define ADPCTL_ADPENA (1 << 20) 388 #define ADPCTL_ADPRES (1 << 19) 389 #define ADPCTL_ENASNS (1 << 18) 390 #define ADPCTL_ENAPRB (1 << 17) 391 #define ADPCTL_RTIM_MASK (0x7ff << 6) 392 #define ADPCTL_RTIM_SHIFT 6 393 #define ADPCTL_PRB_PER_MASK (0x3 << 4) 394 #define ADPCTL_PRB_PER_SHIFT 4 395 #define ADPCTL_PRB_DELTA_MASK (0x3 << 2) 396 #define ADPCTL_PRB_DELTA_SHIFT 2 397 #define ADPCTL_PRB_DSCHRG_MASK (0x3 << 0) 398 #define ADPCTL_PRB_DSCHRG_SHIFT 0 399 400 #define HPTXFSIZ HSOTG_REG(0x100) 401 /* Use FIFOSIZE_* constants to access this register */ 402 403 #define DPTXFSIZN(_a) HSOTG_REG(0x104 + (((_a) - 1) * 4)) 404 /* Use FIFOSIZE_* constants to access this register */ 405 406 /* These apply to the GNPTXFSIZ, HPTXFSIZ and DPTXFSIZN registers */ 407 #define FIFOSIZE_DEPTH_MASK (0xffff << 16) 408 #define FIFOSIZE_DEPTH_SHIFT 16 409 #define FIFOSIZE_STARTADDR_MASK (0xffff << 0) 410 #define FIFOSIZE_STARTADDR_SHIFT 0 411 #define FIFOSIZE_DEPTH_GET(_x) (((_x) >> 16) & 0xffff) 412 413 /* Device mode registers */ 414 415 #define DCFG HSOTG_REG(0x800) 416 #define DCFG_EPMISCNT_MASK (0x1f << 18) 417 #define DCFG_EPMISCNT_SHIFT 18 418 #define DCFG_EPMISCNT_LIMIT 0x1f 419 #define DCFG_EPMISCNT(_x) ((_x) << 18) 420 #define DCFG_PERFRINT_MASK (0x3 << 11) 421 #define DCFG_PERFRINT_SHIFT 11 422 #define DCFG_PERFRINT_LIMIT 0x3 423 #define DCFG_PERFRINT(_x) ((_x) << 11) 424 #define DCFG_DEVADDR_MASK (0x7f << 4) 425 #define DCFG_DEVADDR_SHIFT 4 426 #define DCFG_DEVADDR_LIMIT 0x7f 427 #define DCFG_DEVADDR(_x) ((_x) << 4) 428 #define DCFG_NZ_STS_OUT_HSHK (1 << 2) 429 #define DCFG_DEVSPD_MASK (0x3 << 0) 430 #define DCFG_DEVSPD_SHIFT 0 431 #define DCFG_DEVSPD_HS 0 432 #define DCFG_DEVSPD_FS 1 433 #define DCFG_DEVSPD_LS 2 434 #define DCFG_DEVSPD_FS48 3 435 436 #define DCTL HSOTG_REG(0x804) 437 #define DCTL_PWRONPRGDONE (1 << 11) 438 #define DCTL_CGOUTNAK (1 << 10) 439 #define DCTL_SGOUTNAK (1 << 9) 440 #define DCTL_CGNPINNAK (1 << 8) 441 #define DCTL_SGNPINNAK (1 << 7) 442 #define DCTL_TSTCTL_MASK (0x7 << 4) 443 #define DCTL_TSTCTL_SHIFT 4 444 #define DCTL_GOUTNAKSTS (1 << 3) 445 #define DCTL_GNPINNAKSTS (1 << 2) 446 #define DCTL_SFTDISCON (1 << 1) 447 #define DCTL_RMTWKUPSIG (1 << 0) 448 449 #define DSTS HSOTG_REG(0x808) 450 #define DSTS_SOFFN_MASK (0x3fff << 8) 451 #define DSTS_SOFFN_SHIFT 8 452 #define DSTS_SOFFN_LIMIT 0x3fff 453 #define DSTS_SOFFN(_x) ((_x) << 8) 454 #define DSTS_ERRATICERR (1 << 3) 455 #define DSTS_ENUMSPD_MASK (0x3 << 1) 456 #define DSTS_ENUMSPD_SHIFT 1 457 #define DSTS_ENUMSPD_HS 0 458 #define DSTS_ENUMSPD_FS 1 459 #define DSTS_ENUMSPD_LS 2 460 #define DSTS_ENUMSPD_FS48 3 461 #define DSTS_SUSPSTS (1 << 0) 462 463 #define DIEPMSK HSOTG_REG(0x810) 464 #define DIEPMSK_TXFIFOEMPTY (1 << 7) 465 #define DIEPMSK_INEPNAKEFFMSK (1 << 6) 466 #define DIEPMSK_INTKNEPMISMSK (1 << 5) 467 #define DIEPMSK_INTKNTXFEMPMSK (1 << 4) 468 #define DIEPMSK_TIMEOUTMSK (1 << 3) 469 #define DIEPMSK_AHBERRMSK (1 << 2) 470 #define DIEPMSK_EPDISBLDMSK (1 << 1) 471 #define DIEPMSK_XFERCOMPLMSK (1 << 0) 472 473 #define DOEPMSK HSOTG_REG(0x814) 474 #define DOEPMSK_BACK2BACKSETUP (1 << 6) 475 #define DOEPMSK_OUTTKNEPDISMSK (1 << 4) 476 #define DOEPMSK_SETUPMSK (1 << 3) 477 #define DOEPMSK_AHBERRMSK (1 << 2) 478 #define DOEPMSK_EPDISBLDMSK (1 << 1) 479 #define DOEPMSK_XFERCOMPLMSK (1 << 0) 480 481 #define DAINT HSOTG_REG(0x818) 482 #define DAINTMSK HSOTG_REG(0x81C) 483 #define DAINT_OUTEP_SHIFT 16 484 #define DAINT_OUTEP(_x) (1 << ((_x) + 16)) 485 #define DAINT_INEP(_x) (1 << (_x)) 486 487 #define DTKNQR1 HSOTG_REG(0x820) 488 #define DTKNQR2 HSOTG_REG(0x824) 489 #define DTKNQR3 HSOTG_REG(0x830) 490 #define DTKNQR4 HSOTG_REG(0x834) 491 492 #define DVBUSDIS HSOTG_REG(0x828) 493 #define DVBUSPULSE HSOTG_REG(0x82C) 494 495 #define DIEPCTL0 HSOTG_REG(0x900) 496 #define DIEPCTL(_a) HSOTG_REG(0x900 + ((_a) * 0x20)) 497 498 #define DOEPCTL0 HSOTG_REG(0xB00) 499 #define DOEPCTL(_a) HSOTG_REG(0xB00 + ((_a) * 0x20)) 500 501 /* EP0 specialness: 502 * bits[29..28] - reserved (no SetD0PID, SetD1PID) 503 * bits[25..22] - should always be zero, this isn't a periodic endpoint 504 * bits[10..0] - MPS setting different for EP0 505 */ 506 #define D0EPCTL_MPS_MASK (0x3 << 0) 507 #define D0EPCTL_MPS_SHIFT 0 508 #define D0EPCTL_MPS_64 0 509 #define D0EPCTL_MPS_32 1 510 #define D0EPCTL_MPS_16 2 511 #define D0EPCTL_MPS_8 3 512 513 #define DXEPCTL_EPENA (1 << 31) 514 #define DXEPCTL_EPDIS (1 << 30) 515 #define DXEPCTL_SETD1PID (1 << 29) 516 #define DXEPCTL_SETODDFR (1 << 29) 517 #define DXEPCTL_SETD0PID (1 << 28) 518 #define DXEPCTL_SETEVENFR (1 << 28) 519 #define DXEPCTL_SNAK (1 << 27) 520 #define DXEPCTL_CNAK (1 << 26) 521 #define DXEPCTL_TXFNUM_MASK (0xf << 22) 522 #define DXEPCTL_TXFNUM_SHIFT 22 523 #define DXEPCTL_TXFNUM_LIMIT 0xf 524 #define DXEPCTL_TXFNUM(_x) ((_x) << 22) 525 #define DXEPCTL_STALL (1 << 21) 526 #define DXEPCTL_SNP (1 << 20) 527 #define DXEPCTL_EPTYPE_MASK (0x3 << 18) 528 #define DXEPCTL_EPTYPE_CONTROL (0x0 << 18) 529 #define DXEPCTL_EPTYPE_ISO (0x1 << 18) 530 #define DXEPCTL_EPTYPE_BULK (0x2 << 18) 531 #define DXEPCTL_EPTYPE_INTERRUPT (0x3 << 18) 532 533 #define DXEPCTL_NAKSTS (1 << 17) 534 #define DXEPCTL_DPID (1 << 16) 535 #define DXEPCTL_EOFRNUM (1 << 16) 536 #define DXEPCTL_USBACTEP (1 << 15) 537 #define DXEPCTL_NEXTEP_MASK (0xf << 11) 538 #define DXEPCTL_NEXTEP_SHIFT 11 539 #define DXEPCTL_NEXTEP_LIMIT 0xf 540 #define DXEPCTL_NEXTEP(_x) ((_x) << 11) 541 #define DXEPCTL_MPS_MASK (0x7ff << 0) 542 #define DXEPCTL_MPS_SHIFT 0 543 #define DXEPCTL_MPS_LIMIT 0x7ff 544 #define DXEPCTL_MPS(_x) ((_x) << 0) 545 546 #define DIEPINT(_a) HSOTG_REG(0x908 + ((_a) * 0x20)) 547 #define DOEPINT(_a) HSOTG_REG(0xB08 + ((_a) * 0x20)) 548 #define DXEPINT_SETUP_RCVD (1 << 15) 549 #define DXEPINT_INEPNAKEFF (1 << 6) 550 #define DXEPINT_BACK2BACKSETUP (1 << 6) 551 #define DXEPINT_INTKNEPMIS (1 << 5) 552 #define DXEPINT_INTKNTXFEMP (1 << 4) 553 #define DXEPINT_OUTTKNEPDIS (1 << 4) 554 #define DXEPINT_TIMEOUT (1 << 3) 555 #define DXEPINT_SETUP (1 << 3) 556 #define DXEPINT_AHBERR (1 << 2) 557 #define DXEPINT_EPDISBLD (1 << 1) 558 #define DXEPINT_XFERCOMPL (1 << 0) 559 560 #define DIEPTSIZ0 HSOTG_REG(0x910) 561 #define DIEPTSIZ0_PKTCNT_MASK (0x3 << 19) 562 #define DIEPTSIZ0_PKTCNT_SHIFT 19 563 #define DIEPTSIZ0_PKTCNT_LIMIT 0x3 564 #define DIEPTSIZ0_PKTCNT(_x) ((_x) << 19) 565 #define DIEPTSIZ0_XFERSIZE_MASK (0x7f << 0) 566 #define DIEPTSIZ0_XFERSIZE_SHIFT 0 567 #define DIEPTSIZ0_XFERSIZE_LIMIT 0x7f 568 #define DIEPTSIZ0_XFERSIZE(_x) ((_x) << 0) 569 570 #define DOEPTSIZ0 HSOTG_REG(0xB10) 571 #define DOEPTSIZ0_SUPCNT_MASK (0x3 << 29) 572 #define DOEPTSIZ0_SUPCNT_SHIFT 29 573 #define DOEPTSIZ0_SUPCNT_LIMIT 0x3 574 #define DOEPTSIZ0_SUPCNT(_x) ((_x) << 29) 575 #define DOEPTSIZ0_PKTCNT (1 << 19) 576 #define DOEPTSIZ0_XFERSIZE_MASK (0x7f << 0) 577 #define DOEPTSIZ0_XFERSIZE_SHIFT 0 578 579 #define DIEPTSIZ(_a) HSOTG_REG(0x910 + ((_a) * 0x20)) 580 #define DOEPTSIZ(_a) HSOTG_REG(0xB10 + ((_a) * 0x20)) 581 #define DXEPTSIZ_MC_MASK (0x3 << 29) 582 #define DXEPTSIZ_MC_SHIFT 29 583 #define DXEPTSIZ_MC_LIMIT 0x3 584 #define DXEPTSIZ_MC(_x) ((_x) << 29) 585 #define DXEPTSIZ_PKTCNT_MASK (0x3ff << 19) 586 #define DXEPTSIZ_PKTCNT_SHIFT 19 587 #define DXEPTSIZ_PKTCNT_LIMIT 0x3ff 588 #define DXEPTSIZ_PKTCNT_GET(_v) (((_v) >> 19) & 0x3ff) 589 #define DXEPTSIZ_PKTCNT(_x) ((_x) << 19) 590 #define DXEPTSIZ_XFERSIZE_MASK (0x7ffff << 0) 591 #define DXEPTSIZ_XFERSIZE_SHIFT 0 592 #define DXEPTSIZ_XFERSIZE_LIMIT 0x7ffff 593 #define DXEPTSIZ_XFERSIZE_GET(_v) (((_v) >> 0) & 0x7ffff) 594 #define DXEPTSIZ_XFERSIZE(_x) ((_x) << 0) 595 596 #define DIEPDMA(_a) HSOTG_REG(0x914 + ((_a) * 0x20)) 597 #define DOEPDMA(_a) HSOTG_REG(0xB14 + ((_a) * 0x20)) 598 599 #define DTXFSTS(_a) HSOTG_REG(0x918 + ((_a) * 0x20)) 600 601 #define PCGCTL HSOTG_REG(0x0e00) 602 #define PCGCTL_IF_DEV_MODE (1 << 31) 603 #define PCGCTL_P2HD_PRT_SPD_MASK (0x3 << 29) 604 #define PCGCTL_P2HD_PRT_SPD_SHIFT 29 605 #define PCGCTL_P2HD_DEV_ENUM_SPD_MASK (0x3 << 27) 606 #define PCGCTL_P2HD_DEV_ENUM_SPD_SHIFT 27 607 #define PCGCTL_MAC_DEV_ADDR_MASK (0x7f << 20) 608 #define PCGCTL_MAC_DEV_ADDR_SHIFT 20 609 #define PCGCTL_MAX_TERMSEL (1 << 19) 610 #define PCGCTL_MAX_XCVRSELECT_MASK (0x3 << 17) 611 #define PCGCTL_MAX_XCVRSELECT_SHIFT 17 612 #define PCGCTL_PORT_POWER (1 << 16) 613 #define PCGCTL_PRT_CLK_SEL_MASK (0x3 << 14) 614 #define PCGCTL_PRT_CLK_SEL_SHIFT 14 615 #define PCGCTL_ESS_REG_RESTORED (1 << 13) 616 #define PCGCTL_EXTND_HIBER_SWITCH (1 << 12) 617 #define PCGCTL_EXTND_HIBER_PWRCLMP (1 << 11) 618 #define PCGCTL_ENBL_EXTND_HIBER (1 << 10) 619 #define PCGCTL_RESTOREMODE (1 << 9) 620 #define PCGCTL_RESETAFTSUSP (1 << 8) 621 #define PCGCTL_DEEP_SLEEP (1 << 7) 622 #define PCGCTL_PHY_IN_SLEEP (1 << 6) 623 #define PCGCTL_ENBL_SLEEP_GATING (1 << 5) 624 #define PCGCTL_RSTPDWNMODULE (1 << 3) 625 #define PCGCTL_PWRCLMP (1 << 2) 626 #define PCGCTL_GATEHCLK (1 << 1) 627 #define PCGCTL_STOPPCLK (1 << 0) 628 629 #define EPFIFO(_a) HSOTG_REG(0x1000 + ((_a) * 0x1000)) 630 631 /* Host Mode Registers */ 632 633 #define HCFG HSOTG_REG(0x0400) 634 #define HCFG_MODECHTIMEN (1 << 31) 635 #define HCFG_PERSCHEDENA (1 << 26) 636 #define HCFG_FRLISTEN_MASK (0x3 << 24) 637 #define HCFG_FRLISTEN_SHIFT 24 638 #define HCFG_FRLISTEN_8 (0 << 24) 639 #define FRLISTEN_8_SIZE 8 640 #define HCFG_FRLISTEN_16 (1 << 24) 641 #define FRLISTEN_16_SIZE 16 642 #define HCFG_FRLISTEN_32 (2 << 24) 643 #define FRLISTEN_32_SIZE 32 644 #define HCFG_FRLISTEN_64 (3 << 24) 645 #define FRLISTEN_64_SIZE 64 646 #define HCFG_DESCDMA (1 << 23) 647 #define HCFG_RESVALID_MASK (0xff << 8) 648 #define HCFG_RESVALID_SHIFT 8 649 #define HCFG_ENA32KHZ (1 << 7) 650 #define HCFG_FSLSSUPP (1 << 2) 651 #define HCFG_FSLSPCLKSEL_MASK (0x3 << 0) 652 #define HCFG_FSLSPCLKSEL_SHIFT 0 653 #define HCFG_FSLSPCLKSEL_30_60_MHZ 0 654 #define HCFG_FSLSPCLKSEL_48_MHZ 1 655 #define HCFG_FSLSPCLKSEL_6_MHZ 2 656 657 #define HFIR HSOTG_REG(0x0404) 658 #define HFIR_FRINT_MASK (0xffff << 0) 659 #define HFIR_FRINT_SHIFT 0 660 #define HFIR_RLDCTRL (1 << 16) 661 662 #define HFNUM HSOTG_REG(0x0408) 663 #define HFNUM_FRREM_MASK (0xffff << 16) 664 #define HFNUM_FRREM_SHIFT 16 665 #define HFNUM_FRNUM_MASK (0xffff << 0) 666 #define HFNUM_FRNUM_SHIFT 0 667 #define HFNUM_MAX_FRNUM 0x3fff 668 669 #define HPTXSTS HSOTG_REG(0x0410) 670 #define TXSTS_QTOP_ODD (1 << 31) 671 #define TXSTS_QTOP_CHNEP_MASK (0xf << 27) 672 #define TXSTS_QTOP_CHNEP_SHIFT 27 673 #define TXSTS_QTOP_TOKEN_MASK (0x3 << 25) 674 #define TXSTS_QTOP_TOKEN_SHIFT 25 675 #define TXSTS_QTOP_TERMINATE (1 << 24) 676 #define TXSTS_QSPCAVAIL_MASK (0xff << 16) 677 #define TXSTS_QSPCAVAIL_SHIFT 16 678 #define TXSTS_FSPCAVAIL_MASK (0xffff << 0) 679 #define TXSTS_FSPCAVAIL_SHIFT 0 680 681 #define HAINT HSOTG_REG(0x0414) 682 #define HAINTMSK HSOTG_REG(0x0418) 683 #define HFLBADDR HSOTG_REG(0x041c) 684 685 #define HPRT0 HSOTG_REG(0x0440) 686 #define HPRT0_SPD_MASK (0x3 << 17) 687 #define HPRT0_SPD_SHIFT 17 688 #define HPRT0_SPD_HIGH_SPEED 0 689 #define HPRT0_SPD_FULL_SPEED 1 690 #define HPRT0_SPD_LOW_SPEED 2 691 #define HPRT0_TSTCTL_MASK (0xf << 13) 692 #define HPRT0_TSTCTL_SHIFT 13 693 #define HPRT0_PWR (1 << 12) 694 #define HPRT0_LNSTS_MASK (0x3 << 10) 695 #define HPRT0_LNSTS_SHIFT 10 696 #define HPRT0_RST (1 << 8) 697 #define HPRT0_SUSP (1 << 7) 698 #define HPRT0_RES (1 << 6) 699 #define HPRT0_OVRCURRCHG (1 << 5) 700 #define HPRT0_OVRCURRACT (1 << 4) 701 #define HPRT0_ENACHG (1 << 3) 702 #define HPRT0_ENA (1 << 2) 703 #define HPRT0_CONNDET (1 << 1) 704 #define HPRT0_CONNSTS (1 << 0) 705 706 #define HCCHAR(_ch) HSOTG_REG(0x0500 + 0x20 * (_ch)) 707 #define HCCHAR_CHENA (1 << 31) 708 #define HCCHAR_CHDIS (1 << 30) 709 #define HCCHAR_ODDFRM (1 << 29) 710 #define HCCHAR_DEVADDR_MASK (0x7f << 22) 711 #define HCCHAR_DEVADDR_SHIFT 22 712 #define HCCHAR_MULTICNT_MASK (0x3 << 20) 713 #define HCCHAR_MULTICNT_SHIFT 20 714 #define HCCHAR_EPTYPE_MASK (0x3 << 18) 715 #define HCCHAR_EPTYPE_SHIFT 18 716 #define HCCHAR_LSPDDEV (1 << 17) 717 #define HCCHAR_EPDIR (1 << 15) 718 #define HCCHAR_EPNUM_MASK (0xf << 11) 719 #define HCCHAR_EPNUM_SHIFT 11 720 #define HCCHAR_MPS_MASK (0x7ff << 0) 721 #define HCCHAR_MPS_SHIFT 0 722 723 #define HCSPLT(_ch) HSOTG_REG(0x0504 + 0x20 * (_ch)) 724 #define HCSPLT_SPLTENA (1 << 31) 725 #define HCSPLT_COMPSPLT (1 << 16) 726 #define HCSPLT_XACTPOS_MASK (0x3 << 14) 727 #define HCSPLT_XACTPOS_SHIFT 14 728 #define HCSPLT_XACTPOS_MID 0 729 #define HCSPLT_XACTPOS_END 1 730 #define HCSPLT_XACTPOS_BEGIN 2 731 #define HCSPLT_XACTPOS_ALL 3 732 #define HCSPLT_HUBADDR_MASK (0x7f << 7) 733 #define HCSPLT_HUBADDR_SHIFT 7 734 #define HCSPLT_PRTADDR_MASK (0x7f << 0) 735 #define HCSPLT_PRTADDR_SHIFT 0 736 737 #define HCINT(_ch) HSOTG_REG(0x0508 + 0x20 * (_ch)) 738 #define HCINTMSK(_ch) HSOTG_REG(0x050c + 0x20 * (_ch)) 739 #define HCINTMSK_RESERVED14_31 (0x3ffff << 14) 740 #define HCINTMSK_FRM_LIST_ROLL (1 << 13) 741 #define HCINTMSK_XCS_XACT (1 << 12) 742 #define HCINTMSK_BNA (1 << 11) 743 #define HCINTMSK_DATATGLERR (1 << 10) 744 #define HCINTMSK_FRMOVRUN (1 << 9) 745 #define HCINTMSK_BBLERR (1 << 8) 746 #define HCINTMSK_XACTERR (1 << 7) 747 #define HCINTMSK_NYET (1 << 6) 748 #define HCINTMSK_ACK (1 << 5) 749 #define HCINTMSK_NAK (1 << 4) 750 #define HCINTMSK_STALL (1 << 3) 751 #define HCINTMSK_AHBERR (1 << 2) 752 #define HCINTMSK_CHHLTD (1 << 1) 753 #define HCINTMSK_XFERCOMPL (1 << 0) 754 755 #define HCTSIZ(_ch) HSOTG_REG(0x0510 + 0x20 * (_ch)) 756 #define TSIZ_DOPNG (1 << 31) 757 #define TSIZ_SC_MC_PID_MASK (0x3 << 29) 758 #define TSIZ_SC_MC_PID_SHIFT 29 759 #define TSIZ_SC_MC_PID_DATA0 0 760 #define TSIZ_SC_MC_PID_DATA2 1 761 #define TSIZ_SC_MC_PID_DATA1 2 762 #define TSIZ_SC_MC_PID_MDATA 3 763 #define TSIZ_SC_MC_PID_SETUP 3 764 #define TSIZ_PKTCNT_MASK (0x3ff << 19) 765 #define TSIZ_PKTCNT_SHIFT 19 766 #define TSIZ_NTD_MASK (0xff << 8) 767 #define TSIZ_NTD_SHIFT 8 768 #define TSIZ_SCHINFO_MASK (0xff << 0) 769 #define TSIZ_SCHINFO_SHIFT 0 770 #define TSIZ_XFERSIZE_MASK (0x7ffff << 0) 771 #define TSIZ_XFERSIZE_SHIFT 0 772 773 #define HCDMA(_ch) HSOTG_REG(0x0514 + 0x20 * (_ch)) 774 775 #define HCDMAB(_ch) HSOTG_REG(0x051c + 0x20 * (_ch)) 776 777 #define HCFIFO(_ch) HSOTG_REG(0x1000 + 0x1000 * (_ch)) 778 779 /** 780 * struct dwc2_hcd_dma_desc - Host-mode DMA descriptor structure 781 * 782 * @status: DMA descriptor status quadlet 783 * @buf: DMA descriptor data buffer pointer 784 * 785 * DMA Descriptor structure contains two quadlets: 786 * Status quadlet and Data buffer pointer. 787 */ 788 struct dwc2_hcd_dma_desc { 789 u32 status; 790 u32 buf; 791 }; 792 793 #define HOST_DMA_A (1 << 31) 794 #define HOST_DMA_STS_MASK (0x3 << 28) 795 #define HOST_DMA_STS_SHIFT 28 796 #define HOST_DMA_STS_PKTERR (1 << 28) 797 #define HOST_DMA_EOL (1 << 26) 798 #define HOST_DMA_IOC (1 << 25) 799 #define HOST_DMA_SUP (1 << 24) 800 #define HOST_DMA_ALT_QTD (1 << 23) 801 #define HOST_DMA_QTD_OFFSET_MASK (0x3f << 17) 802 #define HOST_DMA_QTD_OFFSET_SHIFT 17 803 #define HOST_DMA_ISOC_NBYTES_MASK (0xfff << 0) 804 #define HOST_DMA_ISOC_NBYTES_SHIFT 0 805 #define HOST_DMA_NBYTES_MASK (0x1ffff << 0) 806 #define HOST_DMA_NBYTES_SHIFT 0 807 808 #define MAX_DMA_DESC_SIZE 131071 809 #define MAX_DMA_DESC_NUM_GENERIC 64 810 #define MAX_DMA_DESC_NUM_HS_ISOC 256 811 812 #endif /* __DWC2_HW_H__ */ 813