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Searched refs:GPRs (Results 1 – 25 of 155) sorted by relevance

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/netbsd/external/gpl3/gcc.old/dist/gcc/config/frv/
H A Dfrv.opt146 Only use 32 GPRs.
150 Use 64 GPRs.
207 Enable setting GPRs to the result of comparisons.
/netbsd/external/gpl3/gcc/dist/gcc/config/frv/
H A Dfrv.opt146 Only use 32 GPRs.
150 Use 64 GPRs.
207 Enable setting GPRs to the result of comparisons.
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
H A DSystemZCallingConv.td209 // Even though 3 GPRs, 4 FPRs, and 8 VRs may be used,
212 // GPRs 1-3. FP values and vector-type arguments are instead passed in FPRs
263 // Non fixed floats are passed in GPRs
264 // Promote f32 to f64, if it needs to be passed in GPRs.
266 // Assign f64 varargs to their proper GPRs.
/netbsd/external/gpl3/gdb/dist/gas/testsuite/gas/ppc/
H A Dvle-mult-ld-st-insns.s5 # e_lmvgprw, e_stmvgprw - load/store multiple volatile GPRs (r0, r3:r12)
/netbsd/external/gpl3/gdb.old/dist/gas/testsuite/gas/ppc/
H A Dvle-mult-ld-st-insns.s5 # e_lmvgprw, e_stmvgprw - load/store multiple volatile GPRs (r0, r3:r12)
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMRegisterInfo.td255 // GPRs without the PC. Some ARM instructions do not allow the PC in
267 // GPRs without the PC but with APSR. Some instructions allow accessing the
278 // GPRs without the PC and SP registers but with APSR. Used by CLRM instruction.
325 // GPRs without the PC and SP but with APSR_NZCV.Some instructions allow
515 // Pseudo-registers representing even-odd pairs of GPRs from R1 to R13/SP.
516 // These are needed by instructions (e.g. ldrexd/strexd) requiring even-odd GPRs.
524 // Register class representing a pair of even-odd GPRs.
529 // Register class representing a pair of even-odd GPRs, except (R12, SP).
H A DARMCallingConv.td36 // f64 and v2f64 are passed in adjacent GPRs, possibly split onto the stack
133 // i64/f64 is passed in even pairs of GPRs
/netbsd/external/gpl3/binutils.old/dist/cpu/
H A Dor1kcommon.cpu105 ; mapped to GPRs
119 ; mapped to GPRs
152 ; mapped to GPRs
172 ; mapped to GPRs
/netbsd/external/gpl3/gdb/dist/cpu/
H A Dor1kcommon.cpu105 ; mapped to GPRs
138 ; mapped to GPRs
158 ; mapped to GPRs
/netbsd/external/gpl3/binutils/dist/cpu/
H A Dor1kcommon.cpu105 ; mapped to GPRs
138 ; mapped to GPRs
158 ; mapped to GPRs
/netbsd/external/gpl3/gdb.old/dist/cpu/
H A Dor1kcommon.cpu105 ; mapped to GPRs
138 ; mapped to GPRs
158 ; mapped to GPRs
/netbsd/external/gpl3/gcc/dist/gcc/config/rs6000/
H A Dpcrel-opt.md131 ;; PCREL_OPT modes that are optimized for loading or storing GPRs.
141 ;; PCREL_OPT load operation of GPRs. Operand 4 (the register used to hold the
H A Drs6000-modes.def81 /* Replacement for TImode that only is allowed in GPRs. We also use PTImode
/netbsd/external/gpl3/gcc.old/dist/gcc/config/rs6000/
H A Drs6000-modes.def81 /* Replacement for TImode that only is allowed in GPRs. We also use PTImode
H A Drs6000.md414 ; of whole values in GPRs.
447 ; SImode or DImode, even if DImode doesn't fit in GPRs.
705 ;; For the GPRs we use 3 constraints for register outputs, two that are the
4972 ;; register allocator would typically move the entire _Float128 item to GPRs (2
4975 ;; After register allocation, if the _Float128 had originally been in GPRs, the
5823 ;; vector registers, so we need to do direct moves to the GPRs, but SImode
6299 ; hit. We will split after reload to avoid the trip through the GPRs
7021 ;; stores, and transfers within GPRs are assumed to be safe.
7483 ;; stores, and transfers within GPRs are assumed to be safe.
8613 ;; Move 128 bit values from GPRs to VSX registers in 64-bit mode
[all …]
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoD.td311 // Moves two GPRs to an FPR.
317 // Moves an FPR to two GPRs.
H A DRISCV.td206 "Implements RV32E (provides 16 rather than 32 GPRs)">;
/netbsd/external/apache2/llvm/dist/clang/include/clang/Basic/
H A Darm_cde.td60 // CX* instructions operating on GPRs
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86CallingConv.td645 // The first 4 MMX vector arguments are passed in GPRs.
649 // GPRs or on the stack.
1109 // GPRs are preserved.
1119 // All GPRs - except r11
H A DX86RegisterInfo.td430 // GR64 - 64-bit GPRs. This oddly includes RIP, which isn't accurate, since
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCCallingConv.td253 // in a GPR (or in the parameter list area if all GPRs are allocated) from the
H A DREADME.txt324 LR would be in a separate register class from the GPRs. The class of LR would be
H A DPPCISelLowering.cpp6661 ArrayRef<MCPhysReg> GPRs = IsPPC64 ? GPR_64 : GPR_32; in CC_AIX() local
6663 unsigned NextRegIndex = State.getFirstUnallocated(GPRs); in CC_AIX()
6666 while (NextRegIndex != GPRs.size() && in CC_AIX()
6667 !isGPRShadowAligned(GPRs[NextRegIndex], VecAlign)) { in CC_AIX()
6669 unsigned Reg = State.AllocateReg(GPRs); in CC_AIX()
6673 NextRegIndex = State.getFirstUnallocated(GPRs); in CC_AIX()
6685 State.AllocateReg(GPRs); in CC_AIX()
6696 if (NextRegIndex == GPRs.size()) { in CC_AIX()
6705 if (GPRs[NextRegIndex] == PPC::R9) { in CC_AIX()
6728 const unsigned Reg = State.AllocateReg(GPRs); in CC_AIX()
/netbsd/external/gpl3/gcc.old/dist/gcc/config/mips/
H A Dloongson-mmi.md192 ;; GPRs instead of FPRs.
/netbsd/external/gpl3/gcc/dist/gcc/config/mips/
H A Dloongson-mmi.md192 ;; GPRs instead of FPRs.

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