Searched refs:INVALIDATE_ALL_L1_TLBS (Results 1 – 17 of 17) sorted by relevance
| /netbsd/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| H A D | amdgpu_gfxhub_v1_0.c | 162 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); in gfxhub_v1_0_init_cache_regs()
|
| H A D | amdgpu_gfxhub_v2_0.c | 158 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); in gfxhub_v2_0_init_cache_regs()
|
| H A D | amdgpu_mmhub_v2_0.c | 145 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); in mmhub_v2_0_init_cache_regs()
|
| H A D | amdgpu_mmhub_v1_0.c | 182 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); in mmhub_v1_0_init_cache_regs()
|
| H A D | amdgpu_gmc_v7_0.c | 656 tmp = REG_SET_FIELD(0, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); in gmc_v7_0_gart_enable()
|
| H A D | amdgpu_mmhub_v9_4.c | 239 INVALIDATE_ALL_L1_TLBS, 1); in mmhub_v9_4_init_cache_regs()
|
| H A D | sid.h | 383 #define INVALIDATE_ALL_L1_TLBS (1 << 0) macro
|
| H A D | amdgpu_gmc_v8_0.c | 878 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); in gmc_v8_0_gart_enable()
|
| /netbsd/sys/external/bsd/drm2/dist/drm/radeon/ |
| H A D | rv770d.h | 650 #define INVALIDATE_ALL_L1_TLBS (1 << 0) macro
|
| H A D | nid.h | 120 #define INVALIDATE_ALL_L1_TLBS (1 << 0) macro
|
| H A D | sid.h | 381 #define INVALIDATE_ALL_L1_TLBS (1 << 0) macro
|
| H A D | cikd.h | 499 #define INVALIDATE_ALL_L1_TLBS (1 << 0) macro
|
| H A D | evergreend.h | 1158 #define INVALIDATE_ALL_L1_TLBS (1 << 0) macro
|
| H A D | r600d.h | 595 #define INVALIDATE_ALL_L1_TLBS (1 << 0) macro
|
| H A D | radeon_ni.c | 1307 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE); in cayman_pcie_gart_enable()
|
| H A D | radeon_si.c | 4318 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE); in si_pcie_gart_enable()
|
| H A D | radeon_cik.c | 5472 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE); in cik_pcie_gart_enable()
|