| /netbsd/sys/arch/mac68k/mac68k/ |
| H A D | intr.c | 119 ipl2psl_table[IPL_SCHED] = (PSL_S | PSL_IPL6); in intr_init()
125 ipl2psl_table[IPL_SCHED] = (PSL_S | PSL_IPL3); in intr_init()
130 ipl2psl_table[IPL_SCHED] = (PSL_S | PSL_IPL4); in intr_init()
159 if (ipl2psl_table[IPL_VM] > ipl2psl_table[IPL_SCHED]) in intr_computeipl()
160 ipl2psl_table[IPL_SCHED] = ipl2psl_table[IPL_VM]; in intr_computeipl()
162 if (ipl2psl_table[IPL_SCHED] > ipl2psl_table[IPL_HIGH]) in intr_computeipl()
163 ipl2psl_table[IPL_HIGH] = ipl2psl_table[IPL_SCHED]; in intr_computeipl()
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| /netbsd/sys/arch/sparc/include/ |
| H A D | intr.h | 46 #define IPL_SCHED 11 /* scheduler */ macro
53 #define IPL_FD IPL_SCHED
54 #define IPL_TS102 IPL_SCHED
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| /netbsd/sys/arch/mips/cavium/ |
| H A D | octeon_intr.c | 84 [IPL_SCHED] = MIPS_SOFT_INT_MASK | MIPS_INT_MASK_0
181 .ih_ipl = IPL_SCHED,
188 [IPI_SHOOTDOWN] = IPL_SCHED,
380 case IPL_SCHED: in octeon_intr_establish()
443 case IPL_SCHED: in octeon_intr_disestablish()
545 KASSERTMSG((mbox_mask & __BITS(31,16)) == 0 || ci->ci_cpl >= IPL_SCHED, in octeon_ipi_intr()
602 const u_int ipi_shift = ipi_prio[req] == IPL_SCHED ? 16 : 0; in octeon_send_ipi()
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| /netbsd/sys/arch/arm/arm32/ |
| H A D | intr.c | 66 spl_masks[IPL_SCHED] = irqmasks[IPL_SCHED]; in set_spl_masks()
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| /netbsd/sys/sys/ |
| H A D | intr.h | 85 #define IPL_AUDIO IPL_SCHED
86 #define IPL_CLOCK IPL_SCHED
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| /netbsd/sys/arch/or1k/include/ |
| H A D | intr.h | 56 #define IPL_SCHED 6 /* clock interrupt */ macro
115 return _splraise(IPL_SCHED); in splsched()
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| /netbsd/sys/arch/arm/ep93xx/ |
| H A D | ep93xx_intr.c | 161 vic1_imask[IPL_SCHED] |= vic1_imask[IPL_VM]; in ep93xx_intr_calculate_masks()
162 vic2_imask[IPL_SCHED] |= vic2_imask[IPL_VM]; in ep93xx_intr_calculate_masks()
167 vic1_imask[IPL_HIGH] |= vic1_imask[IPL_SCHED]; in ep93xx_intr_calculate_masks()
168 vic2_imask[IPL_HIGH] |= vic2_imask[IPL_SCHED]; in ep93xx_intr_calculate_masks()
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| /netbsd/sys/arch/evbmips/evbmips/ |
| H A D | interrupt.c | 84 KASSERTMSG(ipl == IPL_SCHED, in cpu_intr()
86 __func__, ipl, IPL_SCHED); in cpu_intr()
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| /netbsd/sys/arch/arm/ixp12x0/ |
| H A D | ixp12x0_intr.c | 218 imask[IPL_SCHED] |= imask[IPL_VM]; in ixp12x0_intr_calculate_masks()
219 pci_imask[IPL_SCHED] |= pci_imask[IPL_VM]; in ixp12x0_intr_calculate_masks()
224 imask[IPL_HIGH] |= imask[IPL_SCHED]; in ixp12x0_intr_calculate_masks()
225 pci_imask[IPL_HIGH] |= pci_imask[IPL_SCHED]; in ixp12x0_intr_calculate_masks()
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| /netbsd/sys/arch/mips/include/ |
| H A D | intr.h | 49 #define IPL_SCHED (IPL_VM+1) macro
50 #define IPL_DDB (IPL_SCHED+1)
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| /netbsd/sys/arch/riscv/include/ |
| H A D | intr.h | 49 #define IPL_SCHED (IPL_VM + 1) macro
51 #define IPL_HIGH (IPL_SCHED + 1)
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| /netbsd/sys/arch/powerpc/include/booke/ |
| H A D | intr.h | 47 #define IPL_SCHED 6 /* clock */ macro
165 return splraise(IPL_SCHED); in splsched()
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| /netbsd/sys/dev/dtv/ |
| H A D | dtv_device.c | 110 mutex_init(&ds->ds_egress_lock, MUTEX_DEFAULT, IPL_SCHED); in dtv_attach()
111 mutex_init(&ds->ds_ingress_lock, MUTEX_DEFAULT, IPL_SCHED); in dtv_attach()
121 mutex_init(&sc->sc_demux_lock, MUTEX_DEFAULT, IPL_SCHED); in dtv_attach()
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| /netbsd/sys/arch/sparc/sparc/ |
| H A D | timer_msiiep.c | 181 sched_cookie = sparc_softintr_establish(IPL_SCHED, schedintr, NULL); in timerattach_msiiep()
289 if (CLKF_LOPRI(frame, IPL_SCHED)) { in statintr_msiiep()
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| H A D | timer_sun4m.c | 216 if (CLKF_LOPRI(frame, IPL_SCHED)) { in statintr_4m()
225 raise_ipi(&cpuinfo, IPL_SCHED); /* sched_cookie->pil */ in statintr_4m()
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| /netbsd/sys/arch/mips/rmi/ |
| H A D | rmixl_intr.c | 455 void *ih = rmixl_vec_establish(vec, 0, IPL_SCHED, NULL, NULL, false); in rmixl_intr_init_clk()
473 void * const ih = rmixl_vec_establish(vec, -1, IPL_SCHED, in rmixl_intr_init_ipi()
983 KASSERT(ci->ci_cpl >= IPL_SCHED); in rmixl_ipi_intr()
1053 IPL_SCHED, ipl_eimr_map[IPL_SCHED]); in rmixl_ipl_eimr_map_print()
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| /netbsd/sys/arch/sgimips/sgimips/ |
| H A D | machdep.c | 137 [IPL_SCHED] = MIPS_INT_MASK_4|MIPS_INT_MASK_2|
146 [IPL_SCHED] = MIPS_INT_MASK_4|MIPS_INT_MASK_3|MIPS_INT_MASK_2|
157 [IPL_SCHED] = MIPS_INT_MASK,
164 [IPL_SCHED] = MIPS_INT_MASK_5|MIPS_INT_MASK_0|MIPS_SOFT_INT_MASK,
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| /netbsd/sys/arch/evbarm/ifpga/ |
| H A D | ifpga_intr.c | 176 ifpga_imask[IPL_SCHED] |= ifpga_imask[IPL_VM]; in ifpga_intr_calculate_masks()
177 ifpga_imask[IPL_HIGH] |= ifpga_imask[IPL_SCHED]; in ifpga_intr_calculate_masks()
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| /netbsd/sys/arch/riscv/riscv/ |
| H A D | spl.S | 171 li t1, IPL_SCHED
172 INT_L t0, _C_LABEL(ipl_sie_map) + SZINT * IPL_SCHED
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| /netbsd/sys/arch/arm/xscale/ |
| H A D | pxa2x0_intr.c | 242 pxa2x0_imask[IPL_SCHED] &= pxa2x0_imask[IPL_VM]; in pxa2x0_update_intr_masks()
243 pxa2x0_imask[IPL_HIGH] &= pxa2x0_imask[IPL_SCHED]; in pxa2x0_update_intr_masks()
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| H A D | becc_icu.c | 200 becc_imask[IPL_SCHED] |= becc_imask[IPL_VM]; in becc_intr_calculate_masks()
201 becc_imask[IPL_HIGH] |= becc_imask[IPL_SCHED]; in becc_intr_calculate_masks()
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| /netbsd/sys/arch/usermode/include/ |
| H A D | intrdefs.h | 38 #define IPL_SCHED 6 macro
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| /netbsd/sys/arch/shark/include/ |
| H A D | intr.h | 45 #define IPL_SCHED 6 macro
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| /netbsd/sys/arch/acorn32/include/ |
| H A D | intr.h | 49 #define IPL_SCHED 6 macro
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| /netbsd/sys/arch/arm/footbridge/ |
| H A D | footbridge_irqhandler.c | 148 footbridge_imask[IPL_SCHED] |= footbridge_imask[IPL_VM]; in footbridge_intr_calculate_masks()
149 footbridge_imask[IPL_HIGH] |= footbridge_imask[IPL_SCHED]; in footbridge_intr_calculate_masks()
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