| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/X86/MCTargetDesc/ |
| H A D | X86MCCodeEmitter.cpp | 137 ImmOffset = CDisp8 - Value; in isDispOrCDisp8()
299 emitConstant(DispOp.getImm() + ImmOffset, Size, OS); in emitImmediate()
312 assert(ImmOffset == 0); in emitImmediate()
344 ImmOffset -= 4; in emitImmediate()
352 ImmOffset -= 2; in emitImmediate()
354 ImmOffset -= 1; in emitImmediate()
356 if (ImmOffset) in emitImmediate()
579 int ImmOffset = 0; in emitMemModRMByte() local
583 ImmOffset); in emitMemModRMByte()
606 int ImmOffset = 0; in emitMemModRMByte() local
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPURegisterBankInfo.cpp | 1339 uint32_t SOffset, ImmOffset; in setBufferOffsets() local
1358 uint32_t SOffset, ImmOffset; in setBufferOffsets() local
1451 int64_t ImmOffset = 0; in applyMappingSBufferLoad() local
1688 unsigned ImmOffset; in splitBufferOffsets() local
1695 if (ImmOffset != 0) { in splitBufferOffsets()
1704 ImmOffset -= Overflow; in splitBufferOffsets()
1706 Overflow += ImmOffset; in splitBufferOffsets()
1707 ImmOffset = 0; in splitBufferOffsets()
1710 C1 = ImmOffset; in splitBufferOffsets()
1768 unsigned ImmOffset; in selectStoreIntrinsic() local
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| H A D | AMDGPUISelDAGToDAG.cpp | 196 SDValue &SOffset, SDValue &ImmOffset) const;
1548 ImmOffset = CurDAG->getTargetConstant(Imm & 4095, DL, MVT::i16); in SelectMUBUFScratchOffen()
1586 ImmOffset = CurDAG->getTargetConstant(0, DL, MVT::i16); in SelectMUBUFScratchOffen()
1784 int64_t ImmOffset = 0; in SelectGlobalSAddr() local
1797 ImmOffset = COffsetVal; in SelectGlobalSAddr()
1854 Offset = CurDAG->getTargetConstant(ImmOffset, SDLoc(), MVT::i16); in SelectGlobalSAddr()
1870 Offset = CurDAG->getTargetConstant(ImmOffset, SDLoc(), MVT::i16); in SelectGlobalSAddr()
2491 int ImmOffset = 0; in SelectDS_GWS() local
2507 ImmOffset = ConstOffset->getZExtValue(); in SelectDS_GWS()
2510 ImmOffset = BaseOffset.getConstantOperandVal(1); in SelectDS_GWS()
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| H A D | AMDGPUInstructionSelector.cpp | 1334 unsigned ImmOffset; in selectDSGWSIntrinsic() local
1360 std::tie(BaseOffset, ImmOffset) = in selectDSGWSIntrinsic()
1398 MIB.addImm(ImmOffset) in selectDSGWSIntrinsic()
3521 int64_t ImmOffset = 0; in selectGlobalSAddr() local
3531 ImmOffset = ConstOffset; in selectGlobalSAddr()
3605 MIB.addImm(ImmOffset); in selectGlobalSAddr()
3638 int64_t ImmOffset = 0; in selectScratchSAddr() local
3648 ImmOffset = ConstOffset; in selectScratchSAddr()
4067 if (SIInstrInfo::isLegalMUBUFImmOffset(ImmOffset)) in splitIllegalMUBUFOffset()
4074 .addImm(ImmOffset); in splitIllegalMUBUFOffset()
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| H A D | AMDGPULegalizerInfo.cpp | 3543 unsigned ImmOffset = TotalConstOffset; in splitBufferOffsets() local
3556 unsigned Overflow = ImmOffset & ~MaxImm; in splitBufferOffsets()
3557 ImmOffset -= Overflow; in splitBufferOffsets()
3559 Overflow += ImmOffset; in splitBufferOffsets()
3560 ImmOffset = 0; in splitBufferOffsets()
3675 unsigned ImmOffset; in legalizeBufferStore() local
3735 .addImm(ImmOffset); // offset(imm) in legalizeBufferStore()
3783 unsigned ImmOffset; in legalizeBufferLoad() local
3838 .addImm(ImmOffset); // offset(imm) in legalizeBufferLoad()
3980 unsigned ImmOffset; in legalizeBufferAtomic() local
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| H A D | AMDGPUInstructionSelector.h | 251 Register &SOffset, int64_t &ImmOffset) const;
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| H A D | SIISelLowering.cpp | 7827 unsigned ImmOffset = C1->getZExtValue(); in splitBufferOffsets() local
7835 unsigned Overflow = ImmOffset & ~MaxImm; in splitBufferOffsets()
7836 ImmOffset -= Overflow; in splitBufferOffsets()
7838 Overflow += ImmOffset; in splitBufferOffsets()
7839 ImmOffset = 0; in splitBufferOffsets()
7868 uint32_t SOffset, ImmOffset; in setBufferOffsets() local
7869 if (AMDGPU::splitMUBUFOffset(Imm, SOffset, ImmOffset, Subtarget, in setBufferOffsets()
7873 Offsets[2] = DAG.getTargetConstant(ImmOffset, DL, MVT::i32); in setBufferOffsets()
7874 return SOffset + ImmOffset; in setBufferOffsets()
7880 uint32_t SOffset, ImmOffset; in setBufferOffsets() local
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCFrameLowering.cpp | 857 const int ImmOffset = MFI.getObjectOffset(SaveIndex); in emitPrologue() local
858 assert((ImmOffset <= -8 && ImmOffset >= -512) && in emitPrologue()
860 assert(((ImmOffset & 0x7) == 0) && in emitPrologue()
864 .addImm(ImmOffset) in emitPrologue()
1859 const int ImmOffset = MFI.getObjectOffset(SaveIndex); in emitEpilogue() local
1860 assert((ImmOffset <= -8 && ImmOffset >= -512) && in emitEpilogue()
1862 assert(((ImmOffset & 0x7) == 0) && in emitEpilogue()
1866 .addImm(ImmOffset) in emitEpilogue()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64ExpandPseudoInsts.cpp | 644 int ImmOffset = MI.getOperand(2).getImm() + Offset; in expandSVESpillFill() local
646 assert(ImmOffset >= -256 && ImmOffset < 256 && in expandSVESpillFill()
653 .addImm(ImmOffset); in expandSVESpillFill()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/Utils/ |
| H A D | AMDGPUBaseInfo.h | 889 bool splitMUBUFOffset(uint32_t Imm, uint32_t &SOffset, uint32_t &ImmOffset,
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| H A D | AMDGPUBaseInfo.cpp | 1890 bool splitMUBUFOffset(uint32_t Imm, uint32_t &SOffset, uint32_t &ImmOffset, in splitMUBUFOffset() argument
1924 ImmOffset = Imm; in splitMUBUFOffset()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 3828 SDValue Base, RegOffset, ImmOffset; in Select() local
3831 SelectAddrMode3(Addr, Base, RegOffset, ImmOffset); in Select()
3840 SDValue Ops[] = {Base, RegOffset, ImmOffset, Chain}; in Select()
3857 SDValue Base, RegOffset, ImmOffset; in Select() local
3860 SelectAddrMode3(Addr, Base, RegOffset, ImmOffset); in Select()
3871 SDValue Ops[] = {SDValue(RegPair, 0), Base, RegOffset, ImmOffset, Chain}; in Select()
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