| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/Lanai/ |
| H A D | LanaiSchedule.td | 55 def LdSt : ProcResource<1> { let BufferSize = 0; }
64 def : WriteRes<WriteLD, [LdSt]> { let Latency = 2; }
65 def : WriteRes<WriteST, [LdSt]> { let Latency = 2; }
66 def : WriteRes<WriteLDSW, [LdSt]> { let Latency = 2; }
67 def : WriteRes<WriteSTSW, [LdSt]> { let Latency = 4; }
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| H A D | LanaiInstrInfo.cpp | 758 const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, in getMemOperandWithOffsetWidth() argument
762 if (LdSt.getNumOperands() != 4) in getMemOperandWithOffsetWidth()
764 if (!LdSt.getOperand(1).isReg() || !LdSt.getOperand(2).isImm() || in getMemOperandWithOffsetWidth()
765 !(LdSt.getOperand(3).isImm() && LdSt.getOperand(3).getImm() == LPAC::ADD)) in getMemOperandWithOffsetWidth()
768 switch (LdSt.getOpcode()) { in getMemOperandWithOffsetWidth()
789 BaseOp = &LdSt.getOperand(1); in getMemOperandWithOffsetWidth()
790 Offset = LdSt.getOperand(2).getImm(); in getMemOperandWithOffsetWidth()
799 const MachineInstr &LdSt, SmallVectorImpl<const MachineOperand *> &BaseOps, in getMemOperandsWithOffsetWidth() argument
802 switch (LdSt.getOpcode()) { in getMemOperandsWithOffsetWidth()
816 if (!getMemOperandWithOffsetWidth(LdSt, BaseOp, Offset, Width, TRI)) in getMemOperandsWithOffsetWidth()
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| H A D | LanaiInstrInfo.h | 71 const MachineInstr &LdSt,
76 bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt,
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfo.cpp | 899 const MachineInstr &LdSt, const MachineOperand *&BaseReg, int64_t &Offset, in getMemOperandWithOffsetWidth() argument
901 if (!LdSt.mayLoadOrStore()) in getMemOperandWithOffsetWidth()
907 if (LdSt.getNumExplicitOperands() != 3) in getMemOperandWithOffsetWidth()
909 if (!LdSt.getOperand(1).isReg() || !LdSt.getOperand(2).isImm()) in getMemOperandWithOffsetWidth()
912 if (!LdSt.hasOneMemOperand()) in getMemOperandWithOffsetWidth()
915 Width = (*LdSt.memoperands_begin())->getSize(); in getMemOperandWithOffsetWidth()
916 BaseReg = &LdSt.getOperand(1); in getMemOperandWithOffsetWidth()
917 Offset = LdSt.getOperand(2).getImm(); in getMemOperandWithOffsetWidth()
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| H A D | RISCVInstrInfo.h | 95 bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt,
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.cpp | 248 if (!LdSt.mayLoadOrStore()) in getMemOperandsWithOffsetWidth()
251 unsigned Opc = LdSt.getOpcode(); in getMemOperandsWithOffsetWidth()
256 if (isDS(LdSt)) { in getMemOperandsWithOffsetWidth()
291 if (LdSt.mayLoad()) in getMemOperandsWithOffsetWidth()
294 assert(LdSt.mayStore()); in getMemOperandsWithOffsetWidth()
318 if (isMUBUF(LdSt) || isMTBUF(LdSt)) { in getMemOperandsWithOffsetWidth()
341 Width = getOpSize(LdSt, DataOpIdx); in getMemOperandsWithOffsetWidth()
345 if (isMIMG(LdSt)) { in getMemOperandsWithOffsetWidth()
359 Width = getOpSize(LdSt, DataOpIdx); in getMemOperandsWithOffsetWidth()
363 if (isSMRD(LdSt)) { in getMemOperandsWithOffsetWidth()
[all …]
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| H A D | SIInstrInfo.h | 189 const MachineInstr &LdSt,
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 2751 if (LdSt.hasOrderedMemoryRef() || LdSt.getNumExplicitOperands() != 3) in isLdStSafeToCluster()
2754 if (LdSt.getOperand(2).isFI()) in isLdStSafeToCluster()
2760 if (LdSt.modifiesRegister(LdSt.getOperand(2).getReg(), TRI)) in isLdStSafeToCluster()
5450 if (!LdSt.mayLoadOrStore() || LdSt.getNumExplicitOperands() != 3) in getMemOperandWithOffsetWidth()
5454 if (!LdSt.getOperand(1).isImm() || in getMemOperandWithOffsetWidth()
5455 (!LdSt.getOperand(2).isReg() && !LdSt.getOperand(2).isFI())) in getMemOperandWithOffsetWidth()
5457 if (!LdSt.getOperand(1).isImm() || in getMemOperandWithOffsetWidth()
5458 (!LdSt.getOperand(2).isReg() && !LdSt.getOperand(2).isFI())) in getMemOperandWithOffsetWidth()
5461 if (!LdSt.hasOneMemOperand()) in getMemOperandWithOffsetWidth()
5465 Offset = LdSt.getOperand(1).getImm(); in getMemOperandWithOffsetWidth()
[all …]
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| H A D | PPCInstrInfo.h | 532 bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt,
540 const MachineInstr &LdSt,
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 2517 if (!LdSt.mayLoadOrStore()) in getMemOperandsWithOffsetWidth()
2552 if (LdSt.getNumExplicitOperands() == 3) { in getMemOperandWithOffsetWidth()
2554 if ((!LdSt.getOperand(1).isReg() && !LdSt.getOperand(1).isFI()) || in getMemOperandWithOffsetWidth()
2555 !LdSt.getOperand(2).isImm()) in getMemOperandWithOffsetWidth()
2559 if (!LdSt.getOperand(1).isReg() || in getMemOperandWithOffsetWidth()
2560 (!LdSt.getOperand(2).isReg() && !LdSt.getOperand(2).isFI()) || in getMemOperandWithOffsetWidth()
2561 !LdSt.getOperand(3).isImm()) in getMemOperandWithOffsetWidth()
2578 if (LdSt.getNumExplicitOperands() == 3) { in getMemOperandWithOffsetWidth()
2579 BaseOp = &LdSt.getOperand(1); in getMemOperandWithOffsetWidth()
2583 BaseOp = &LdSt.getOperand(2); in getMemOperandWithOffsetWidth()
[all …]
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| H A D | AArch64InstrInfo.h | 143 MachineOperand &getMemOpBaseRegImmOfsOffsetOperand(MachineInstr &LdSt) const;
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| H A D | AArch64SchedTSV110.td | 128 // MicroOp Count/Types: #(ALU|AB|MDU|FSU1|FSU2|LdSt|ALUAB|F|FLdSt)
131 // 1 micro-ops to be issued down one ALU pipe, six MDU pipes and four LdSt pipes.
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.h | 208 const MachineInstr &LdSt,
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| H A D | HexagonInstrInfo.cpp | 2974 const MachineInstr &LdSt, SmallVectorImpl<const MachineOperand *> &BaseOps, in getMemOperandsWithOffsetWidth() argument
2978 const MachineOperand *BaseOp = getBaseAndOffset(LdSt, Offset, Width); in getMemOperandsWithOffsetWidth()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86InstrInfo.h | 332 const MachineInstr &LdSt,
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMScheduleR52.td | 551 foreach Num = 1-32 in { // reserve LdSt resource, no dual-issue
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| H A D | ARMISelDAGToDAG.cpp | 1070 LSBaseSDNode *LdSt = cast<LSBaseSDNode>(Op); in SelectAddrMode6Offset() local
1071 ISD::MemIndexedMode AM = LdSt->getAddressingMode(); in SelectAddrMode6Offset()
1076 if (NC->getZExtValue() * 8 == LdSt->getMemoryVT().getSizeInBits()) in SelectAddrMode6Offset()
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