/netbsd/external/apache2/llvm/dist/llvm/include/llvm/MC/ |
H A D | MCInstrDesc.h | 141 namespace MCID { 386 return Flags & (1ULL << MCID::ExtractSubreg); in isExtractSubregLike() 410 return Flags & (1ULL << MCID::VariadicOpsAreDefs); in variadicOpsAreDefs() 419 return Flags & (1ULL << MCID::Authenticated); in isAuthenticated() 439 return Flags & (1ULL << MCID::MayRaiseFPException); in mayRaiseFPException() 455 return Flags & (1ULL << MCID::UnmodeledSideEffects); in hasUnmodeledSideEffects() 489 return Flags & (1ULL << MCID::ConvertibleTo3Addr); in isConvertibleTo3Addr() 501 return Flags & (1ULL << MCID::UsesCustomInserter); in usesCustomInsertionHook() 517 return Flags & (1ULL << MCID::Rematerializable); in isRematerializable() 538 return Flags & (1ULL << MCID::ExtraSrcRegAllocReq); in hasExtraSrcRegAllocReq() [all …]
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/netbsd/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
H A D | MachineInstrBuilder.h | 329 const MCInstrDesc &MCID) { in BuildMI() argument 349 MachineInstr *MI = MF.CreateMachineInstr(MCID, DL); in BuildMI() 365 MachineInstr *MI = MF.CreateMachineInstr(MCID, DL); in BuildMI() 383 return BuildMI(BB, *I, DL, MCID, DestReg); in BuildMI() 392 const MCInstrDesc &MCID) { in BuildMI() argument 394 MachineInstr *MI = MF.CreateMachineInstr(MCID, DL); in BuildMI() 402 const MCInstrDesc &MCID) { in BuildMI() argument 404 MachineInstr *MI = MF.CreateMachineInstr(MCID, DL); in BuildMI() 422 return BuildMI(BB, *I, DL, MCID); in BuildMI() 429 return BuildMI(*BB, BB->end(), DL, MCID); in BuildMI() [all …]
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H A D | MachineInstr.h | 799 return hasProperty(MCID::Pseudo, Type); 803 return hasProperty(MCID::Return, Type); 813 return hasProperty(MCID::Call, Type); 828 return hasProperty(MCID::Barrier, Type); 845 return hasProperty(MCID::Branch, Type); 882 return hasProperty(MCID::Compare, Type); 888 return hasProperty(MCID::MoveImm, Type); 894 return hasProperty(MCID::MoveReg, Type); 899 return hasProperty(MCID::Bitcast, Type); 904 return hasProperty(MCID::Select, Type); [all …]
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
H A D | PPCHazardRecognizers.cpp | 30 if (!MCID) in isLoadAfterStore() 33 if (!MCID->mayLoad()) in isLoadAfterStore() 56 if (!MCID) in isBCTRAfterSet() 59 if (!MCID->isBranch()) in isBCTRAfterSet() 90 unsigned IIC = MCID->getSchedClass(); in mustComeFirst() 149 if (MCID && mustComeFirst(MCID, NSlots) && CurSlots) in ShouldPreferAnother() 176 if (MCID) { in EmitInstruction() 197 if (MCID->isBranch()) in EmitInstruction() 284 isLoad = MCID.mayLoad(); in GetInstrType() 285 isStore = MCID.mayStore(); in GetInstrType() [all …]
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/M68k/ |
H A D | M68kInstrBuilder.h | 63 const MCInstrDesc &MCID = MI->getDesc(); variable 65 if (MCID.mayLoad()) 67 if (MCID.mayStore()) 80 const MCInstrDesc &MCID = MI->getDesc(); variable 82 if (MCID.mayLoad()) 84 if (MCID.mayStore())
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/netbsd/external/apache2/llvm/dist/llvm/lib/Transforms/Utils/ |
H A D | ValueMapper.cpp | 88 unsigned MCID : 29; member 161 unsigned MCID); 165 unsigned MCID); 167 unsigned MCID); 168 void scheduleRemapFunction(Function &F, unsigned MCID); 857 CurrentMCID = E.MCID; in flush() 1046 WE.MCID = MCID; in scheduleMapGlobalInitializer() 1062 WE.MCID = MCID; in scheduleMapAppendingVariable() 1078 WE.MCID = MCID; in scheduleMapGlobalIndirectSymbol() 1090 WE.MCID = MCID; in scheduleRemapFunction() [all …]
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
H A D | Thumb2SizeReduction.cpp | 656 if (MCID.hasOptionalDef() && in ReduceSpecial() 815 const MCInstrDesc &MCID = MI->getDesc(); in ReduceTo2Addr() local 816 if (MCID.hasOptionalDef()) { in ReduceTo2Addr() 839 unsigned NumOps = MCID.getNumOperands(); in ReduceTo2Addr() 875 const MCInstrDesc &MCID = MI->getDesc(); in ReduceToNarrow() local 877 if (MCID.OpInfo[i].isPredicate()) in ReduceToNarrow() 908 if (MCID.hasOptionalDef()) { in ReduceToNarrow() 930 if (MCID.getOpcode() == ARM::t2TEQrr) { in ReduceToNarrow() 946 unsigned NumOps = MCID.getNumOperands(); in ReduceToNarrow() 952 MCID.getOpcode() == ARM::t2SXTB || in ReduceToNarrow() [all …]
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H A D | ARMHazardRecognizer.cpp | 29 const MCInstrDesc &MCID = MI->getDesc(); in hasRAWHazard() local 30 unsigned Domain = MCID.TSFlags & ARMII::DomainMask; in hasRAWHazard() 33 unsigned Opcode = MCID.getOpcode(); in hasRAWHazard() 50 const MCInstrDesc &MCID = MI->getDesc(); in getHazardType() local 51 if (LastMI && (MCID.TSFlags & ARMII::DomainMask) != ARMII::DomainGeneral) { in getHazardType()
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H A D | MLxExpansionPass.cpp | 184 const MCInstrDesc &MCID = MI->getDesc(); in hasRAWHazard() local 185 unsigned Domain = MCID.TSFlags & ARMII::DomainMask; in hasRAWHazard() 188 unsigned Opcode = MCID.getOpcode(); in hasRAWHazard() 339 const MCInstrDesc &MCID = MI->getDesc(); in ExpandFPMLxInstructions() local 346 unsigned Domain = MCID.TSFlags & ARMII::DomainMask; in ExpandFPMLxInstructions() 356 if (!TII->isFpMLxInstruction(MCID.getOpcode(), in ExpandFPMLxInstructions()
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/ |
H A D | NVPTXReplaceImageHandles.cpp | 81 const MCInstrDesc &MCID = MI.getDesc(); in processInstr() local 83 if (MCID.TSFlags & NVPTXII::IsTexFlag) { in processInstr() 89 if (!(MCID.TSFlags & NVPTXII::IsTexModeUnifiedFlag)) { in processInstr() 95 } else if (MCID.TSFlags & NVPTXII::IsSuldMask) { in processInstr() 97 1 << (((MCID.TSFlags & NVPTXII::IsSuldMask) >> NVPTXII::IsSuldShift) - 1); in processInstr() 105 } else if (MCID.TSFlags & NVPTXII::IsSustFlag) { in processInstr() 112 } else if (MCID.TSFlags & NVPTXII::IsSurfTexQueryFlag) { in processInstr()
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/netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
H A D | ScoreboardHazardRecognizer.cpp | 123 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in getHazardType() local 124 if (!MCID) { in getHazardType() 128 unsigned idx = MCID->getSchedClass(); in getHazardType() 178 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in EmitInstruction() local 179 assert(MCID && "The scheduler must filter non-machineinstrs"); in EmitInstruction() 180 if (DAG->TII->isZeroCost(MCID->Opcode)) in EmitInstruction() 187 unsigned idx = MCID->getSchedClass(); in EmitInstruction()
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H A D | MachineInstr.cpp | 105 if (MCID->ImplicitDefs) in addImplicitDefUseOperands() 109 if (MCID->ImplicitUses) in addImplicitDefUseOperands() 125 MCID->getNumImplicitDefs() + MCID->getNumImplicitUses()) { in MachineInstr() 728 if (!MCID->isVariadic()) in getNumExplicitOperands() 746 unsigned NumDefs = MCID->getNumDefs(); in getNumExplicitDefs() 747 if (!MCID->isVariadic()) in getNumExplicitDefs() 1074 const MCInstrDesc &MCID = getDesc(); in findFirstPredOperandIdx() local 1075 if (MCID.isPredicable()) { in findFirstPredOperandIdx() 1077 if (MCID.OpInfo[i].isPredicate()) in findFirstPredOperandIdx() 1499 const MCInstrDesc &MCID = getDesc(); in hasComplexRegisterTies() local [all …]
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H A D | BreakFalseDeps.cpp | 189 const MCInstrDesc &MCID = MI->getDesc(); in processDefs() local 193 for (unsigned i = MCID.getNumDefs(), e = MCID.getNumOperands(); i != e; ++i) { in processDefs() 215 e = MI->isVariadic() ? MI->getNumOperands() : MCID.getNumDefs(); in processDefs()
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H A D | MachineVerifier.cpp | 879 const MCInstrDesc &MCID = MI->getDesc(); in verifyPreISelGenericInstruction() local 903 if (!MCID.OpInfo[I].isGenericType()) in verifyPreISelGenericInstruction() 1599 const MCInstrDesc &MCID = MI->getDesc(); in visitMachineInstrBefore() local 1666 unsigned Opc = MCID.getOpcode(); in visitMachineInstrBefore() 1782 const MCInstrDesc &MCID = MI->getDesc(); in visitMachineOperand() local 1783 unsigned NumDefs = MCID.getNumDefs(); in visitMachineOperand() 1796 } else if (MONum < MCID.getNumOperands()) { in visitMachineOperand() 1863 if (MONum < MCID.getNumDefs()) { in visitMachineOperand() 1897 if (MONum < MCID.getNumOperands()) { in visitMachineOperand() 1977 MONum < MCID.getNumOperands() && in visitMachineOperand() [all …]
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H A D | TargetInstrInfo.cpp | 50 if (OpNum >= MCID.getNumOperands()) in getRegClass() 53 short RegClass = MCID.OpInfo[OpNum].RegClass; in getRegClass() 54 if (MCID.OpInfo[OpNum].isLookupPtrRegClass()) in getRegClass() 170 const MCInstrDesc &MCID = MI.getDesc(); in commuteInstructionImpl() local 171 bool HasDef = MCID.getNumDefs(); in commuteInstructionImpl() 302 const MCInstrDesc &MCID = MI.getDesc(); in findCommutedOpIndices() local 303 if (!MCID.isCommutable()) in findCommutedOpIndices() 308 unsigned CommutableOpIdx1 = MCID.getNumDefs(); in findCommutedOpIndices() 338 const MCInstrDesc &MCID = MI.getDesc(); in PredicateInstruction() local 343 if (MCID.OpInfo[i].isPredicate()) { in PredicateInstruction() [all …]
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/netbsd/external/apache2/llvm/dist/llvm/lib/MCA/ |
H A D | CodeEmitter.cpp | 19 CodeEmitter::getOrCreateEncodingInfo(unsigned MCID) { in getOrCreateEncodingInfo() argument 20 EncodingInfo &EI = Encodings[MCID]; in getOrCreateEncodingInfo() 25 const MCInst &Inst = Sequence[MCID]; in getOrCreateEncodingInfo() 26 MCInst Relaxed(Sequence[MCID]); in getOrCreateEncodingInfo()
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/netbsd/external/bsd/tcpdump/dist/tests/ |
H A D | evb.out | 5 v3len 64, MCID Name Default, rev 0, 12 v3len 64, MCID Name Default, rev 0, 19 v3len 64, MCID Name Default, rev 0, 67 v3len 64, MCID Name Default, rev 0, 74 v3len 64, MCID Name Default, rev 0, 81 v3len 64, MCID Name Default, rev 0, 88 v3len 64, MCID Name Default, rev 0, 95 v3len 64, MCID Name Default, rev 0, 102 v3len 64, MCID Name Default, rev 0, 109 v3len 64, MCID Name Default, rev 0, [all …]
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H A D | spb_bpduv4-v.out | 5 v3len 80, MCID Name IEEE802.1 SPB Default, rev 0, 21 v3len 80, MCID Name IEEE802.1 SPB Default, rev 0, 37 v3len 80, MCID Name IEEE802.1 SPB Default, rev 0, 53 v3len 80, MCID Name IEEE802.1 SPB Default, rev 0, 69 v3len 80, MCID Name IEEE802.1 SPB Default, rev 0, 85 v3len 80, MCID Name IEEE802.1 SPB Default, rev 0, 101 v3len 80, MCID Name IEEE802.1 SPB Default, rev 0, 117 v3len 80, MCID Name IEEE802.1 SPB Default, rev 0, 133 v3len 80, MCID Name IEEE802.1 SPB Default, rev 0, 149 v3len 80, MCID Name IEEE802.1 SPB Default, rev 0, [all …]
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H A D | mstp-v.out | 5 v3len 96, MCID Name Brewery, rev 0, 18 v3len 96, MCID Name Brewery, rev 0, 31 v3len 96, MCID Name Brewery, rev 0, 44 v3len 96, MCID Name Brewery, rev 0, 57 v3len 96, MCID Name Brewery, rev 0, 70 v3len 96, MCID Name Brewery, rev 0, 83 v3len 96, MCID Name Brewery, rev 0, 96 v3len 96, MCID Name Brewery, rev 0, 109 v3len 96, MCID Name Brewery, rev 0, 122 v3len 96, MCID Name Brewery, rev 0,
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
H A D | SystemZInstrBuilder.h | 29 const MCInstrDesc &MCID = MI->getDesc(); in addFrameReference() local 31 if (MCID.mayLoad()) in addFrameReference() 33 if (MCID.mayStore()) in addFrameReference()
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/netbsd/external/apache2/llvm/dist/llvm/include/llvm/MCA/ |
H A D | CodeEmitter.h | 51 EncodingInfo getOrCreateEncodingInfo(unsigned MCID); 59 StringRef getEncoding(unsigned MCID) { in getEncoding() argument 60 EncodingInfo EI = getOrCreateEncodingInfo(MCID); in getEncoding()
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/netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
H A D | ScheduleDAGFast.cpp | 254 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode()); in CopyAndMoveSuccessors() local 255 for (unsigned i = 0; i != MCID.getNumOperands(); ++i) { in CopyAndMoveSuccessors() 256 if (MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1) { in CopyAndMoveSuccessors() 261 if (MCID.isCommutable()) in CopyAndMoveSuccessors() 432 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode()); in getPhysicalRegisterVT() local 433 assert(MCID.ImplicitDefs && "Physical reg def must be in implicit def list!"); in getPhysicalRegisterVT() 434 NumRes = MCID.getNumDefs(); in getPhysicalRegisterVT() 435 for (const MCPhysReg *ImpDef = MCID.getImplicitDefs(); *ImpDef; ++ImpDef) { in getPhysicalRegisterVT() 511 const MCInstrDesc &MCID = TII->get(Node->getMachineOpcode()); in DelayForLiveRegsBottomUp() local 512 if (!MCID.ImplicitDefs) in DelayForLiveRegsBottomUp() [all …]
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/MCTargetDesc/ |
H A D | HexagonMCChecker.cpp | 90 const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MCI); in init() local 95 for (unsigned i = MCID.getNumDefs(); i < MCID.getNumOperands(); ++i) in init() 98 for (unsigned i = 0; i < MCID.getNumImplicitUses(); ++i) in init() 99 initReg(MCI, MCID.getImplicitUses()[i], PredReg, isTrue); in init() 102 if (const MCPhysReg *ImpDef = MCID.getImplicitDefs()) in init() 106 if (Hexagon::R31 != R && MCID.isCall()) in init() 131 for (unsigned i = 0; i < MCID.getNumDefs(); ++i) { in init() 188 for (unsigned i = MCID.getNumDefs(); i < MCID.getNumOperands(); ++i) in init()
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/VE/ |
H A D | LVLGen.cpp | 41 const MCInstrDesc &MCID = TII->get(Opcode); in getVLIndex() local 44 if (HAS_VLINDEX(MCID.TSFlags)) in getVLIndex() 45 return GET_VLINDEX(MCID.TSFlags); in getVLIndex()
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
H A D | AArch64ConditionalCompares.cpp | 632 const MCInstrDesc &MCID = TII->get(Opc); in convert() local 635 MRI->createVirtualRegister(TII->getRegClass(MCID, 0, TRI, *MF)); in convert() 637 BuildMI(*Head, Head->end(), TermDL, MCID) in convert() 644 TII->getRegClass(MCID, 1, TRI, *MF)); in convert() 689 const MCInstrDesc &MCID = TII->get(Opc); in convert() local 691 TII->getRegClass(MCID, 0, TRI, *MF)); in convert() 694 TII->getRegClass(MCID, 1, TRI, *MF)); in convert() 695 MachineInstrBuilder MIB = BuildMI(*Head, CmpMI, CmpMI->getDebugLoc(), MCID) in convert()
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