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Searched refs:MCSchedModel (Results 1 – 25 of 50) sorted by relevance

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/netbsd/external/apache2/llvm/dist/llvm/lib/MC/
H A DMCSchedule.cpp22 static_assert(std::is_pod<MCSchedModel>::value,
24 const MCSchedModel MCSchedModel::Default = {DefaultIssueWidth,
40 int MCSchedModel::computeInstrLatency(const MCSubtargetInfo &STI, in computeInstrLatency()
56 int MCSchedModel::computeInstrLatency(const MCSubtargetInfo &STI, in computeInstrLatency()
62 return MCSchedModel::computeInstrLatency(STI, SCDesc); in computeInstrLatency()
67 int MCSchedModel::computeInstrLatency(const MCSubtargetInfo &STI, in computeInstrLatency()
82 return MCSchedModel::computeInstrLatency(STI, *SCDesc); in computeInstrLatency()
88 MCSchedModel::getReciprocalThroughput(const MCSubtargetInfo &STI, in getReciprocalThroughput()
91 const MCSchedModel &SM = STI.getSchedModel(); in getReciprocalThroughput()
128 return MCSchedModel::getReciprocalThroughput(STI, *SCDesc); in getReciprocalThroughput()
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H A DMCSubtargetInfo.cpp216 CPUSchedModel = &MCSchedModel::GetDefaultSchedModel(); in InitMCProcessorInfo()
309 const MCSchedModel &MCSubtargetInfo::getSchedModelForCPU(StringRef CPU) const { in getSchedModelForCPU()
321 return MCSchedModel::GetDefaultSchedModel(); in getSchedModelForCPU()
329 const MCSchedModel &SchedModel = getSchedModelForCPU(CPU); in getInstrItineraryForCPU()
/netbsd/external/apache2/llvm/dist/llvm/include/llvm/MCA/Stages/
H A DInOrderIssueStage.h24 struct MCSchedModel;
32 const MCSchedModel &SM;
82 InOrderIssueStage(RegisterFile &PRF, const MCSchedModel &SM, in InOrderIssueStage()
H A DInstructionTables.h29 const MCSchedModel &SM;
34 InstructionTables(const MCSchedModel &Model) in InstructionTables()
/netbsd/external/apache2/llvm/dist/llvm/tools/llvm-mca/Views/
H A DInstructionInfoView.cpp95 const MCSchedModel &SM = STI.getSchedModel(); in collectData()
112 IIVDEntry.Latency = MCSchedModel::computeInstrLatency(STI, SCDesc); in collectData()
114 IIVDEntry.Latency += MCSchedModel::getForwardingDelayCycles( in collectData()
116 IIVDEntry.RThroughput = MCSchedModel::getReciprocalThroughput(STI, SCDesc); in collectData()
H A DSummaryView.h41 const llvm::MCSchedModel &SM;
84 SummaryView(const llvm::MCSchedModel &Model, llvm::ArrayRef<llvm::MCInst> S,
H A DResourcePressureView.cpp27 const MCSchedModel &SM = getSubTargetInfo().getSchedModel(); in ResourcePressureView()
69 const MCSchedModel &SM) { in printColumnNames()
109 const MCSchedModel &SM = getSubTargetInfo().getSchedModel(); in printResourcePressurePerIter()
H A DBottleneckAnalysis.h96 const MCSchedModel &SM;
138 PressureTracker(const MCSchedModel &Model);
H A DRetireControlUnitStatistics.h50 RetireControlUnitStatistics(const MCSchedModel &SM);
H A DSchedulerStatistics.h48 const llvm::MCSchedModel &SM;
/netbsd/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DTargetSchedule.h34 MCSchedModel SchedModel;
50 TargetSchedModel() : SchedModel(MCSchedModel::GetDefaultSchedModel()) {} in TargetSchedModel()
75 const MCSchedModel *getMCSchedModel() const { return &SchedModel; } in getMCSchedModel()
/netbsd/external/apache2/llvm/dist/llvm/include/llvm/MC/
H A DMCSubtargetInfo.h58 const MCSchedModel *SchedModel;
86 const MCSchedModel *CPUSchedModel;
159 const MCSchedModel &getSchedModelForCPU(StringRef CPU) const;
162 const MCSchedModel &getSchedModel() const { return *CPUSchedModel; } in getSchedModel()
H A DMCInstrItineraries.h111 MCSchedModel SchedModel =
112 MCSchedModel::GetDefaultSchedModel(); ///< Basic machine properties.
120 InstrItineraryData(const MCSchedModel &SM, const InstrStage *S, in InstrItineraryData()
H A DMCSchedule.h245 struct MCSchedModel { struct
380 static const MCSchedModel &GetDefaultSchedModel() { return Default; } in GetDefaultSchedModel() argument
381 static const MCSchedModel Default; argument
/netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DTargetSchedule.cpp257 return capLatency(MCSchedModel::computeInstrLatency(*STI, SCDesc)); in computeInstrLatency()
328 return MCSchedModel::getReciprocalThroughput(SchedClass, in computeReciprocalThroughput()
333 return MCSchedModel::getReciprocalThroughput(*STI, *resolveSchedClass(MI)); in computeReciprocalThroughput()
342 return MCSchedModel::getReciprocalThroughput(SchedClass, in computeReciprocalThroughput()
347 return MCSchedModel::getReciprocalThroughput(*STI, SCDesc); in computeReciprocalThroughput()
/netbsd/external/apache2/llvm/dist/llvm/include/llvm/MCA/HardwareUnits/
H A DLSUnit.h225 LSUnitBase(const MCSchedModel &SM, unsigned LoadQueueSize,
446 LSUnit(const MCSchedModel &SM) in LSUnit()
448 LSUnit(const MCSchedModel &SM, unsigned LQ, unsigned SQ) in LSUnit()
450 LSUnit(const MCSchedModel &SM, unsigned LQ, unsigned SQ, bool AssumeNoAlias) in LSUnit()
H A DRegisterFile.h229 void initialize(const MCSchedModel &SM, unsigned NumRegs);
232 RegisterFile(const MCSchedModel &SM, const MCRegisterInfo &mri,
H A DScheduler.h157 Scheduler(const MCSchedModel &Model, LSUnitBase &Lsu) in Scheduler()
160 Scheduler(const MCSchedModel &Model, LSUnitBase &Lsu, in Scheduler()
H A DRetireControlUnit.h80 RetireControlUnit(const MCSchedModel &SM);
/netbsd/external/apache2/llvm/dist/llvm/include/llvm/MCA/
H A DSupport.h94 void computeProcResourceMasks(const MCSchedModel &SM,
108 double computeBlockRThroughput(const MCSchedModel &SM, unsigned DispatchWidth,
/netbsd/external/apache2/llvm/dist/llvm/lib/MCA/
H A DSupport.cpp39 void computeProcResourceMasks(const MCSchedModel &SM, in computeProcResourceMasks()
82 double computeBlockRThroughput(const MCSchedModel &SM, unsigned DispatchWidth, in computeBlockRThroughput()
H A DContext.cpp33 const MCSchedModel &SM = STI.getSchedModel(); in createDefaultPipeline()
73 const MCSchedModel &SM = STI.getSchedModel(); in createInOrderPipeline()
H A DInstrBuilder.cpp33 const MCSchedModel &SM = STI.getSchedModel(); in InstrBuilder()
42 const MCSchedModel &SM = STI.getSchedModel(); in initializeUsedResources()
216 int Latency = MCSchedModel::computeInstrLatency(STI, SCDesc); in computeMaxLatency()
253 const MCSchedModel &SM = STI.getSchedModel(); in populateWrites()
518 const MCSchedModel &SM = STI.getSchedModel(); in createInstrDescImpl()
/netbsd/external/apache2/llvm/dist/llvm/tools/llvm-exegesis/lib/
H A DSchedClassResolution.h35 computeIdealizedProcResPressure(const MCSchedModel &SM,
/netbsd/external/apache2/llvm/dist/llvm/lib/MCA/HardwareUnits/
H A DRegisterFile.cpp62 RegisterFile::RegisterFile(const MCSchedModel &SM, const MCRegisterInfo &mri, in RegisterFile()
70 void RegisterFile::initialize(const MCSchedModel &SM, unsigned NumRegs) { in initialize()
479 const MCSchedModel &SM = STI.getSchedModel(); in collectWrites()
559 const MCSchedModel &SM = STI.getSchedModel(); in addRegisterRead()

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