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Searched refs:MemIndexedMode (Results 1 – 25 of 30) sorted by relevance

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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/AVR/
H A DAVRISelLowering.h108 ISD::MemIndexedMode &AM,
112 SDValue &Offset, ISD::MemIndexedMode &AM,
H A DAVRISelDAGToDAG.cpp123 ISD::MemIndexedMode AM = LD->getAddressingMode(); in selectIndexedLoad()
170 ISD::MemIndexedMode AM = LD->getAddressingMode(); in selectIndexedProgMemLoad()
H A DAVRISelLowering.cpp877 ISD::MemIndexedMode &AM, in getPreIndexedAddressParts()
934 ISD::MemIndexedMode &AM, in getPostIndexedAddressParts()
/netbsd/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DSelectionDAGNodes.h987 static const char* getIndexedModeName(ISD::MemIndexedMode AM);
2221 SDVTList VTs, ISD::MemIndexedMode AM, EVT MemVT,
2234 ISD::MemIndexedMode getAddressingMode() const {
2235 return static_cast<ISD::MemIndexedMode>(LSBaseSDNodeBits.AddressingMode);
2255 ISD::MemIndexedMode AM, ISD::LoadExtType ETy, EVT MemVT,
2283 ISD::MemIndexedMode AM, bool isTrunc, EVT MemVT,
2316 ISD::MemIndexedMode AM, EVT MemVT,
2335 ISD::MemIndexedMode getAddressingMode() const {
2336 return static_cast<ISD::MemIndexedMode>(LSBaseSDNodeBits.AddressingMode);
2357 ISD::MemIndexedMode AM, ISD::LoadExtType ETy,
[all …]
H A DSelectionDAG.h1211 SDValue Offset, ISD::MemIndexedMode AM);
1212 SDValue getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT,
1219 ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT, const SDLoc &dl,
1231 getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT,
1240 SDValue getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT,
1301 SDValue Offset, ISD::MemIndexedMode AM);
1305 MachineMemOperand *MMO, ISD::MemIndexedMode AM,
1308 SDValue Offset, ISD::MemIndexedMode AM);
1311 MachineMemOperand *MMO, ISD::MemIndexedMode AM,
1315 ISD::MemIndexedMode AM);
H A DISDOpcodes.h1290 enum MemIndexedMode { UNINDEXED = 0, PRE_INC, PRE_DEC, POST_INC, POST_DEC }; enum
H A DBasicTTIImpl.h176 static ISD::MemIndexedMode getISDIndexedMode(TTI::MemIndexedMode M) { in getISDIndexedMode()
309 bool isIndexedLoadLegal(TTI::MemIndexedMode M, Type *Ty, in isIndexedLoadLegal()
315 bool isIndexedStoreLegal(TTI::MemIndexedMode M, Type *Ty, in isIndexedStoreLegal()
H A DTargetLowering.h3177 ISD::MemIndexedMode &/*AM*/, in getPreIndexedAddressParts() argument
3188 ISD::MemIndexedMode &/*AM*/, in getPostIndexedAddressParts() argument
/netbsd/external/apache2/llvm/dist/llvm/include/llvm/Analysis/
H A DTargetTransformInfo.h1291 enum MemIndexedMode { enum
1300 bool isIndexedLoadLegal(enum MemIndexedMode Mode, Type *Ty) const;
1303 bool isIndexedStoreLegal(enum MemIndexedMode Mode, Type *Ty) const;
1697 virtual bool isIndexedLoadLegal(MemIndexedMode Mode, Type *Ty) const = 0;
1698 virtual bool isIndexedStoreLegal(MemIndexedMode Mode, Type *Ty) const = 0;
2232 bool isIndexedLoadLegal(MemIndexedMode Mode, Type *Ty) const override { in isIndexedLoadLegal()
2235 bool isIndexedStoreLegal(MemIndexedMode Mode, Type *Ty) const override { in isIndexedStoreLegal()
H A DTargetTransformInfoImpl.h692 bool isIndexedLoadLegal(TTI::MemIndexedMode Mode, Type *Ty, in isIndexedLoadLegal()
697 bool isIndexedStoreLegal(TTI::MemIndexedMode Mode, Type *Ty, in isIndexedStoreLegal()
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.h185 ISD::MemIndexedMode &AM,
H A DMSP430ISelDAGToDAG.cpp299 ISD::MemIndexedMode AM = LD->getAddressingMode(); in isValidIndexedLoad()
H A DMSP430ISelLowering.cpp1337 ISD::MemIndexedMode &AM, in getPostIndexedAddressParts()
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.h1052 ISD::MemIndexedMode &AM, bool &IsInc,
1055 ISD::MemIndexedMode &AM,
1058 SDValue &Offset, ISD::MemIndexedMode &AM,
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMISelLowering.h489 ISD::MemIndexedMode &AM,
496 SDValue &Offset, ISD::MemIndexedMode &AM,
H A DARMISelDAGToDAG.cpp816 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD) in SelectAddrMode2OffsetReg()
852 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD) in SelectAddrMode2OffsetImmPre()
872 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD) in SelectAddrMode2OffsetImm()
951 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD) in SelectAddrMode3Offset()
1071 ISD::MemIndexedMode AM = LdSt->getAddressingMode(); in SelectAddrMode6Offset()
1380 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD) in SelectT2AddrModeImm8Offset()
1432 ISD::MemIndexedMode AM; in SelectT2AddrModeImm7Offset()
1576 ISD::MemIndexedMode AM = LD->getAddressingMode(); in tryARMIndexedLoad()
1656 ISD::MemIndexedMode AM = LD->getAddressingMode(); in tryT1IndexedLoad()
1682 ISD::MemIndexedMode AM = LD->getAddressingMode(); in tryT2IndexedLoad()
[all …]
H A DARMInstrMVE.td7020 ISD::MemIndexedMode AM = cast<MaskedStoreSDNode>(N)->getAddressingMode();
7025 ISD::MemIndexedMode AM = cast<MaskedStoreSDNode>(N)->getAddressingMode();
7104 ISD::MemIndexedMode AM = cast<MaskedStoreSDNode>(N)->getAddressingMode();
7119 ISD::MemIndexedMode AM = cast<MaskedStoreSDNode>(N)->getAddressingMode();
/netbsd/external/apache2/llvm/dist/llvm/lib/Analysis/
H A DTargetTransformInfo.cpp966 bool TargetTransformInfo::isIndexedLoadLegal(MemIndexedMode Mode, in isIndexedLoadLegal()
971 bool TargetTransformInfo::isIndexedStoreLegal(MemIndexedMode Mode, in isIndexedStoreLegal()
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.h272 ISD::MemIndexedMode &AM,
H A DHexagonISelDAGToDAG.cpp450 ISD::MemIndexedMode AM = LD->getAddressingMode(); in SelectLoad()
559 ISD::MemIndexedMode AM = ST->getAddressingMode(); in SelectStore()
H A DHexagonISelLowering.cpp631 SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, in getPostIndexedAddressParts()
/netbsd/external/apache2/llvm/dist/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td1174 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
1185 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
1226 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
1232 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.h803 ISD::MemIndexedMode &AM,
/netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp490 const char *SDNode::getIndexedModeName(ISD::MemIndexedMode AM) { in getIndexedModeName()
H A DSelectionDAG.cpp7268 SDValue SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, in getLoad()
7292 SDValue SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, in getLoad()
7379 ISD::MemIndexedMode AM) { in getIndexedLoad()
7510 ISD::MemIndexedMode AM) { in getIndexedStore()
7540 ISD::MemIndexedMode AM, in getMaskedLoad()
7572 ISD::MemIndexedMode AM) { in getIndexedMaskedLoad()
7585 ISD::MemIndexedMode AM, bool IsTruncating, in getMaskedStore()
7620 ISD::MemIndexedMode AM) { in getIndexedMaskedStore()

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