/netbsd/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
H A D | X86MCInstLower.cpp | 517 unsigned NewOpc; in Lower() local 525 OutMI.setOpcode(NewOpc); in Lower() 549 unsigned NewOpc; in Lower() local 566 OutMI.setOpcode(NewOpc); in Lower() 574 unsigned NewOpc; in Lower() local 580 OutMI.setOpcode(NewOpc); in Lower() 617 unsigned NewOpc; in Lower() local 682 OutMI.setOpcode(NewOpc); in Lower() 689 unsigned NewOpc; in Lower() local 853 unsigned NewOpc; in Lower() local [all …]
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H A D | X86EvexToVex.cpp | 149 static bool performCustomAdjustments(MachineInstr &MI, unsigned NewOpc, in performCustomAdjustments() argument 151 (void)NewOpc; in performCustomAdjustments() 158 assert((NewOpc == X86::VPALIGNRrri || NewOpc == X86::VPALIGNRrmi) && in performCustomAdjustments() 174 assert((NewOpc == X86::VPERM2F128rr || NewOpc == X86::VPERM2I128rr || in performCustomAdjustments() 175 NewOpc == X86::VPERM2F128rm || NewOpc == X86::VPERM2I128rm) && in performCustomAdjustments() 260 unsigned NewOpc = I->VexOpcode; in CompressEvexToVexImpl() local 268 if (!performCustomAdjustments(MI, NewOpc, ST)) in CompressEvexToVexImpl() 271 MI.setDesc(TII->get(NewOpc)); in CompressEvexToVexImpl()
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H A D | X86FixupLEAs.cpp | 598 unsigned NewOpc = getADDrrFromLEA(MI.getOpcode()); in processInstrForSlow3OpLEA() local 604 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpc), DestReg) in processInstrForSlow3OpLEA() 610 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpc), DestReg) in processInstrForSlow3OpLEA() 636 unsigned NewOpc = in processInstrForSlow3OpLEA() local 638 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpc), DestReg) in processInstrForSlow3OpLEA() 642 unsigned NewOpc = getADDriFromLEA(MI.getOpcode(), Offset); in processInstrForSlow3OpLEA() local 643 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpc), DestReg) in processInstrForSlow3OpLEA() 670 unsigned NewOpc = getADDrrFromLEA(MI.getOpcode()); in processInstrForSlow3OpLEA() local 671 NewMI = BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(NewOpc), DestReg) in processInstrForSlow3OpLEA() 693 unsigned NewOpc = getADDrrFromLEA(MI.getOpcode()); in processInstrForSlow3OpLEA() local [all …]
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H A D | X86InstructionSelector.cpp | 531 if (NewOpc == Opc) in selectLoadStoreOp() 537 I.setDesc(TII.get(NewOpc)); in selectLoadStoreOp() 573 I.setDesc(TII.get(NewOpc)); in selectFrameIndexOrGep() 625 I.setDesc(TII.get(NewOpc)); in selectGlobalValue() 655 unsigned NewOpc; in selectConstant() local 658 NewOpc = X86::MOV8ri; in selectConstant() 661 NewOpc = X86::MOV16ri; in selectConstant() 664 NewOpc = X86::MOV32ri; in selectConstant() 669 NewOpc = X86::MOV64ri32; in selectConstant() 671 NewOpc = X86::MOV64ri; in selectConstant() [all …]
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H A D | X86ISelDAGToDAG.cpp | 992 unsigned NewOpc; in PreprocessISelDAG() local 1025 unsigned NewOpc; in PreprocessISelDAG() local 1047 unsigned NewOpc; in PreprocessISelDAG() local 1051 NewOpc = ISD::SIGN_EXTEND; in PreprocessISelDAG() 1053 NewOpc = N->getOpcode() == ISD::ANY_EXTEND in PreprocessISelDAG() 1437 unsigned NewOpc; in PostprocessISelDAG() local 1480 unsigned NewOpc; in PostprocessISelDAG() local 3214 unsigned NewOpc = in foldLoadStoreIntoMemOperand() local 3304 unsigned NewOpc = SelectRegOpcode(Opc); in foldLoadStoreIntoMemOperand() local 3328 NewOpc = SelectImm8Opcode(Opc); in foldLoadStoreIntoMemOperand() [all …]
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/X86/AsmParser/ |
H A D | X86AsmParser.cpp | 3610 unsigned NewOpc; in processInstruction() local 3627 Inst.setOpcode(NewOpc); in processInstruction() 3639 unsigned NewOpc; in processInstruction() local 3645 Inst.setOpcode(NewOpc); in processInstruction() 3660 unsigned NewOpc; in processInstruction() local 3663 case X86::RCR8ri: NewOpc = X86::RCR8r1; break; in processInstruction() 3664 case X86::RCR16ri: NewOpc = X86::RCR16r1; break; in processInstruction() 3665 case X86::RCR32ri: NewOpc = X86::RCR32r1; break; in processInstruction() 3694 TmpInst.setOpcode(NewOpc); in processInstruction() 3713 unsigned NewOpc; in processInstruction() local [all …]
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
H A D | HexagonRDFOpt.cpp | 224 unsigned OpNum, NewOpc; in rewrite() local 227 NewOpc = Hexagon::L2_loadri_io; in rewrite() 231 NewOpc = Hexagon::L2_loadrd_io; in rewrite() 235 NewOpc = Hexagon::V6_vL32b_ai; in rewrite() 239 NewOpc = Hexagon::S2_storeri_io; in rewrite() 243 NewOpc = Hexagon::S2_storerd_io; in rewrite() 247 NewOpc = Hexagon::V6_vS32b_ai; in rewrite() 273 MI.setDesc(HII.get(NewOpc)); in rewrite()
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H A D | HexagonGenPredicate.cpp | 389 unsigned NewOpc = getPredForm(Opc); in convertToPredForm() local 391 if (NewOpc == 0) { in convertToPredForm() 394 NewOpc = Hexagon::C2_not; in convertToPredForm() 397 NewOpc = TargetOpcode::COPY; in convertToPredForm() 424 MachineInstrBuilder MIB = BuildMI(B, MI, DL, TII->get(NewOpc), NewPR.R); in convertToPredForm()
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H A D | HexagonCopyToCombine.cpp | 874 unsigned NewOpc; in emitCombineRR() local 876 NewOpc = Hexagon::A2_combinew; in emitCombineRR() 879 NewOpc = Hexagon::V6_vcombine; in emitCombineRR() 883 BuildMI(*BB, InsertPt, DL, TII->get(NewOpc), DoubleDestReg) in emitCombineRR()
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
H A D | MipsInstrInfo.cpp | 595 MipsInstrInfo::genInstrWithNewOpc(unsigned NewOpc, in genInstrWithNewOpc() argument 617 switch (NewOpc) { in genInstrWithNewOpc() 619 NewOpc = Mips::BEQZC; in genInstrWithNewOpc() 622 NewOpc = Mips::BNEZC; in genInstrWithNewOpc() 625 NewOpc = Mips::BGEZC; in genInstrWithNewOpc() 628 NewOpc = Mips::BLTZC; in genInstrWithNewOpc() 631 NewOpc = Mips::BEQZC64; in genInstrWithNewOpc() 634 NewOpc = Mips::BNEZC64; in genInstrWithNewOpc() 645 if (NewOpc == Mips::JIC || NewOpc == Mips::JIALC || NewOpc == Mips::JIC64 || in genInstrWithNewOpc() 646 NewOpc == Mips::JIALC64) { in genInstrWithNewOpc() [all …]
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H A D | MipsSEInstrInfo.h | 98 unsigned NewOpc) const;
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
H A D | ARMLoadStoreOptimizer.cpp | 1498 unsigned NewOpc; in MergeBaseUpdateLoadStore() local 1541 if (NewOpc == ARM::LDR_PRE_IMM || NewOpc == ARM::LDRB_PRE_IMM) { in MergeBaseUpdateLoadStore() 1635 unsigned NewOpc; in MergeBaseUpdateLSDouble() local 1651 if (NewOpc == ARM::t2LDRD_PRE || NewOpc == ARM::t2LDRD_POST) { in MergeBaseUpdateLSDouble() 1654 assert(NewOpc == ARM::t2STRD_PRE || NewOpc == ARM::t2STRD_POST); in MergeBaseUpdateLSDouble() 1804 unsigned NewOpc = (isLd) in FixInvalidRegPairOp() local 1828 unsigned NewOpc = (isLd) in FixInvalidRegPairOp() local 2268 NewOpc = ARM::LDRD; in CanFormLdStDWord() 2270 NewOpc = ARM::STRD; in CanFormLdStDWord() 2272 NewOpc = ARM::t2LDRDi8; in CanFormLdStDWord() [all …]
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H A D | ARMConstantIslandPass.cpp | 1787 unsigned NewOpc = 0; in optimizeThumb2Instructions() local 1808 if (!NewOpc) in optimizeThumb2Instructions() 1838 unsigned NewOpc = 0; in optimizeThumb2Branches() local 1844 NewOpc = ARM::tB; in optimizeThumb2Branches() 1849 NewOpc = ARM::tBcc; in optimizeThumb2Branches() 1854 if (NewOpc) { in optimizeThumb2Branches() 1872 unsigned NewOpc = 0; in optimizeThumb2Branches() member 1878 ImmCmp.NewOpc = 0; in optimizeThumb2Branches() 1886 unsigned NewOpc = 0; in optimizeThumb2Branches() local 1910 ImmCmp.NewOpc = NewOpc; in optimizeThumb2Branches() [all …]
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H A D | Thumb2InstrInfo.cpp | 576 unsigned NewOpc = isSub ? IsSP ? ARM::t2SUBspImm12 : ARM::t2SUBri12 in rewriteT2FrameIndex() local 578 MI.setDesc(TII.get(NewOpc)); in rewriteT2FrameIndex() 609 unsigned NewOpc = Opcode; in rewriteT2FrameIndex() local 619 NewOpc = immediateOffsetOpcode(Opcode); in rewriteT2FrameIndex() 631 NewOpc = negativeOffsetOpcode(Opcode); in rewriteT2FrameIndex() 636 NewOpc = positiveOffsetOpcode(Opcode); in rewriteT2FrameIndex() 696 if (NewOpc != Opcode) in rewriteT2FrameIndex() 697 MI.setDesc(TII.get(NewOpc)); in rewriteT2FrameIndex() 741 MI.setDesc(TII.get(positiveOffsetOpcode(NewOpc))); in rewriteT2FrameIndex()
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H A D | ARMInstructionSelector.cpp | 899 unsigned NewOpc = selectSimpleExtOpc(I.getOpcode(), SrcSize); in select() local 900 if (NewOpc == I.getOpcode()) in select() 902 I.setDesc(TII.get(NewOpc)); in select() 1095 const auto NewOpc = selectLoadStoreOpCode(I.getOpcode(), RegBank, ValSize); in select() local 1096 if (NewOpc == G_LOAD || NewOpc == G_STORE) in select() 1099 if (ValSize == 1 && NewOpc == Opcodes.STORE8) { in select() 1117 I.setDesc(TII.get(NewOpc)); in select() 1119 if (NewOpc == ARM::LDRH || NewOpc == ARM::STRH) in select()
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H A D | ARMExpandPseudoInsts.cpp | 1916 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc)) in ExpandMI() 1926 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc)) in ExpandMI() 2187 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc), in ExpandMI() 2228 unsigned NewOpc; in ExpandMI() local 2230 case ARM::t2MOVCClsl: NewOpc = ARM::t2LSLri; break; in ExpandMI() 2231 case ARM::t2MOVCClsr: NewOpc = ARM::t2LSRri; break; in ExpandMI() 2232 case ARM::t2MOVCCasr: NewOpc = ARM::t2ASRri; break; in ExpandMI() 2233 case ARM::t2MOVCCror: NewOpc = ARM::t2RORri; break; in ExpandMI() 2236 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc), in ExpandMI() 2505 unsigned NewOpc = ARM::VLDMDIA; in ExpandMI() local [all …]
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H A D | ThumbRegisterInfo.cpp | 404 unsigned NewOpc = convertToNonSPOpcode(Opcode); in rewriteFrameIndex() local 405 if (NewOpc != Opcode && FrameReg != ARM::SP) in rewriteFrameIndex() 406 MI.setDesc(TII.get(NewOpc)); in rewriteFrameIndex()
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/ |
H A D | AArch64PostSelectOptimize.cpp | 143 unsigned NewOpc = getNonFlagSettingVariant(II.getOpcode()); in optimizeNZCVDefs() local 147 if (InsideCmpRange && NewOpc) { in optimizeNZCVDefs() 151 II.setDesc(TII->get(NewOpc)); in optimizeNZCVDefs()
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/Lanai/ |
H A D | LanaiMemAluCombiner.cpp | 252 unsigned NewOpc = mergedOpcode(MemInstr->getOpcode(), AluOffset.isImm()); in insertMergedInstruction() local 255 assert(NewOpc != 0 && "Unknown merged node opcode"); in insertMergedInstruction() 259 BuildMI(*BB, MemInstr, MemInstr->getDebugLoc(), TII->get(NewOpc)); in insertMergedInstruction()
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
H A D | AArch64AdvSIMDScalarPass.cpp | 292 unsigned NewOpc = getTransformOpcode(OldOpc); in transformInstruction() local 293 assert(OldOpc != NewOpc && "transform an instruction to itself?!"); in transformInstruction() 362 BuildMI(*MBB, MI, MI.getDebugLoc(), TII->get(NewOpc), Dst) in transformInstruction()
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H A D | AArch64CondBrTuning.cpp | 100 unsigned NewOpc = TII->convertToFlagSettingOpc(MI.getOpcode(), Is64Bit); in convertToFlagSetting() local 106 TII->get(NewOpc), NewDestReg); in convertToFlagSetting()
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H A D | AArch64FrameLowering.cpp | 894 unsigned NewOpc; in convertCalleeSaveRestoreToSPPrePostIncDec() local 899 NewOpc = AArch64::STPXpre; in convertCalleeSaveRestoreToSPPrePostIncDec() 902 NewOpc = AArch64::STPDpre; in convertCalleeSaveRestoreToSPPrePostIncDec() 905 NewOpc = AArch64::STPQpre; in convertCalleeSaveRestoreToSPPrePostIncDec() 908 NewOpc = AArch64::STRXpre; in convertCalleeSaveRestoreToSPPrePostIncDec() 911 NewOpc = AArch64::STRDpre; in convertCalleeSaveRestoreToSPPrePostIncDec() 914 NewOpc = AArch64::STRQpre; in convertCalleeSaveRestoreToSPPrePostIncDec() 917 NewOpc = AArch64::LDPXpost; in convertCalleeSaveRestoreToSPPrePostIncDec() 920 NewOpc = AArch64::LDPDpost; in convertCalleeSaveRestoreToSPPrePostIncDec() 923 NewOpc = AArch64::LDPQpost; in convertCalleeSaveRestoreToSPPrePostIncDec() [all …]
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUPostLegalizerCombiner.cpp | 235 unsigned NewOpc = AMDGPU::G_AMDGPU_CVT_F32_UBYTE0 + MatchInfo.ShiftOffset / 8; in applyCvtF32UByteN() local 245 assert(MI.getOpcode() != NewOpc); in applyCvtF32UByteN() 246 B.buildInstr(NewOpc, {MI.getOperand(0)}, {CvtSrc}, MI.getFlags()); in applyCvtF32UByteN()
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H A D | SIInstrInfo.cpp | 966 int NewOpc; in commuteOpcode() local 970 if (NewOpc != -1) in commuteOpcode() 972 return pseudoToMCOpcode(NewOpc) != -1 ? NewOpc : -1; in commuteOpcode() 976 if (NewOpc != -1) in commuteOpcode() 978 return pseudoToMCOpcode(NewOpc) != -1 ? NewOpc : -1; in commuteOpcode() 2794 unsigned NewOpc = in FoldImmediate() local 2879 unsigned NewOpc = in FoldImmediate() local 3101 unsigned NewOpc = in convertToThreeAddress() local 3114 unsigned NewOpc = IsFMA in convertToThreeAddress() local 4992 if (NewOpc < 0) in moveFlatAddrToVGPR() [all …]
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/netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeVectorOps.cpp | 684 unsigned NewOpc = Node->getOpcode(); in PromoteFP_TO_INT() local 687 if (NewOpc == ISD::FP_TO_UINT && in PromoteFP_TO_INT() 689 NewOpc = ISD::FP_TO_SINT; in PromoteFP_TO_INT() 691 if (NewOpc == ISD::STRICT_FP_TO_UINT && in PromoteFP_TO_INT() 693 NewOpc = ISD::STRICT_FP_TO_SINT; in PromoteFP_TO_INT() 698 Promoted = DAG.getNode(NewOpc, dl, {NVT, MVT::Other}, in PromoteFP_TO_INT() 702 Promoted = DAG.getNode(NewOpc, dl, NVT, Node->getOperand(0)); in PromoteFP_TO_INT() 709 NewOpc = ISD::AssertZext; in PromoteFP_TO_INT() 711 NewOpc = ISD::AssertSext; in PromoteFP_TO_INT() 713 Promoted = DAG.getNode(NewOpc, dl, NVT, Promoted, in PromoteFP_TO_INT()
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