OP_ENT (reference) in projects: netbsd - OpenGrok search results

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Searched refs:OP_ENT (Results 1 – 12 of 12) sorted by relevance

/netbsd/external/gpl3/gdb/dist/opcodes/
H A D	lm32-opinst.c	35 #define OP_ENT(op) LM32_OPERAND_##op macro 46 { INPUT, "r0", HW_H_GR, CGEN_MODE_SI, OP_ENT (R0), 0, 0 }, 47 { INPUT, "r1", HW_H_GR, CGEN_MODE_SI, OP_ENT (R1), 0, 0 }, 48 { OUTPUT, "r2", HW_H_GR, CGEN_MODE_SI, OP_ENT (R2), 0, 0 }, 54 { INPUT, "r0", HW_H_GR, CGEN_MODE_SI, OP_ENT (R0), 0, 0 }, 55 { OUTPUT, "r1", HW_H_GR, CGEN_MODE_SI, OP_ENT (R1), 0, 0 }, 60 { INPUT, "r0", HW_H_GR, CGEN_MODE_SI, OP_ENT (R0), 0, 0 }, 62 { OUTPUT, "r1", HW_H_GR, CGEN_MODE_SI, OP_ENT (R1), 0, 0 }, 68 { INPUT, "r0", HW_H_GR, CGEN_MODE_SI, OP_ENT (R0), 0, 0 }, 75 { INPUT, "r0", HW_H_GR, CGEN_MODE_SI, OP_ENT (R0), 0, 0 }, [all …]
H A D	m32r-opinst.c	35 #define OP_ENT(op) M32R_OPERAND_##op macro 46 { INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, 47 { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 }, 48 { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, 54 { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 }, 55 { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, 60 { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 }, 67 { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 }, 74 { INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, 81 { INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, [all …]
H A D	or1k-opinst.c	35 #define OP_ENT(op) OR1K_OPERAND_##op macro 54 { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 }, 68 { INPUT, "rB", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RB), 0, 0 }, 76 { INPUT, "rB", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RB), 0, 0 }, 121 { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 }, 128 { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 }, 129 { INPUT, "rB", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RB), 0, 0 }, 136 { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 }, 144 { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 }, 152 { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 }, [all …]
/netbsd/external/gpl3/binutils.old/dist/opcodes/
H A D	lm32-opinst.c	35 #define OP_ENT(op) LM32_OPERAND_##op macro 46 { INPUT, "r0", HW_H_GR, CGEN_MODE_SI, OP_ENT (R0), 0, 0 }, 47 { INPUT, "r1", HW_H_GR, CGEN_MODE_SI, OP_ENT (R1), 0, 0 }, 48 { OUTPUT, "r2", HW_H_GR, CGEN_MODE_SI, OP_ENT (R2), 0, 0 }, 54 { INPUT, "r0", HW_H_GR, CGEN_MODE_SI, OP_ENT (R0), 0, 0 }, 55 { OUTPUT, "r1", HW_H_GR, CGEN_MODE_SI, OP_ENT (R1), 0, 0 }, 60 { INPUT, "r0", HW_H_GR, CGEN_MODE_SI, OP_ENT (R0), 0, 0 }, 62 { OUTPUT, "r1", HW_H_GR, CGEN_MODE_SI, OP_ENT (R1), 0, 0 }, 68 { INPUT, "r0", HW_H_GR, CGEN_MODE_SI, OP_ENT (R0), 0, 0 }, 75 { INPUT, "r0", HW_H_GR, CGEN_MODE_SI, OP_ENT (R0), 0, 0 }, [all …]
H A D	m32r-opinst.c	35 #define OP_ENT(op) M32R_OPERAND_##op macro 46 { INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, 47 { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 }, 48 { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, 54 { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 }, 55 { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, 60 { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 }, 67 { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 }, 74 { INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, 81 { INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, [all …]
H A D	or1k-opinst.c	35 #define OP_ENT(op) OR1K_OPERAND_##op macro 54 { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 }, 68 { INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 }, 76 { INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 }, 121 { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, 128 { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, 129 { INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 }, 136 { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, 144 { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, 152 { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, [all …]
/netbsd/external/gpl3/binutils/dist/opcodes/
H A D	lm32-opinst.c	35 #define OP_ENT(op) LM32_OPERAND_##op macro 46 { INPUT, "r0", HW_H_GR, CGEN_MODE_SI, OP_ENT (R0), 0, 0 }, 47 { INPUT, "r1", HW_H_GR, CGEN_MODE_SI, OP_ENT (R1), 0, 0 }, 48 { OUTPUT, "r2", HW_H_GR, CGEN_MODE_SI, OP_ENT (R2), 0, 0 }, 54 { INPUT, "r0", HW_H_GR, CGEN_MODE_SI, OP_ENT (R0), 0, 0 }, 55 { OUTPUT, "r1", HW_H_GR, CGEN_MODE_SI, OP_ENT (R1), 0, 0 }, 60 { INPUT, "r0", HW_H_GR, CGEN_MODE_SI, OP_ENT (R0), 0, 0 }, 62 { OUTPUT, "r1", HW_H_GR, CGEN_MODE_SI, OP_ENT (R1), 0, 0 }, 68 { INPUT, "r0", HW_H_GR, CGEN_MODE_SI, OP_ENT (R0), 0, 0 }, 75 { INPUT, "r0", HW_H_GR, CGEN_MODE_SI, OP_ENT (R0), 0, 0 }, [all …]
H A D	m32r-opinst.c	35 #define OP_ENT(op) M32R_OPERAND_##op macro 46 { INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, 47 { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 }, 48 { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, 54 { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 }, 55 { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, 60 { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 }, 67 { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 }, 74 { INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, 81 { INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, [all …]
H A D	or1k-opinst.c	35 #define OP_ENT(op) OR1K_OPERAND_##op macro 54 { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 }, 68 { INPUT, "rB", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RB), 0, 0 }, 76 { INPUT, "rB", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RB), 0, 0 }, 121 { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 }, 128 { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 }, 129 { INPUT, "rB", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RB), 0, 0 }, 136 { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 }, 144 { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 }, 152 { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 }, [all …]
/netbsd/external/gpl3/gdb.old/dist/opcodes/
H A D	lm32-opinst.c	35 #define OP_ENT(op) LM32_OPERAND_##op macro 46 { INPUT, "r0", HW_H_GR, CGEN_MODE_SI, OP_ENT (R0), 0, 0 }, 47 { INPUT, "r1", HW_H_GR, CGEN_MODE_SI, OP_ENT (R1), 0, 0 }, 48 { OUTPUT, "r2", HW_H_GR, CGEN_MODE_SI, OP_ENT (R2), 0, 0 }, 54 { INPUT, "r0", HW_H_GR, CGEN_MODE_SI, OP_ENT (R0), 0, 0 }, 55 { OUTPUT, "r1", HW_H_GR, CGEN_MODE_SI, OP_ENT (R1), 0, 0 }, 60 { INPUT, "r0", HW_H_GR, CGEN_MODE_SI, OP_ENT (R0), 0, 0 }, 62 { OUTPUT, "r1", HW_H_GR, CGEN_MODE_SI, OP_ENT (R1), 0, 0 }, 68 { INPUT, "r0", HW_H_GR, CGEN_MODE_SI, OP_ENT (R0), 0, 0 }, 75 { INPUT, "r0", HW_H_GR, CGEN_MODE_SI, OP_ENT (R0), 0, 0 }, [all …]
H A D	m32r-opinst.c	35 #define OP_ENT(op) M32R_OPERAND_##op macro 46 { INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, 47 { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 }, 48 { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, 54 { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 }, 55 { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, 60 { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 }, 67 { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 }, 74 { INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, 81 { INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, [all …]
H A D	or1k-opinst.c	35 #define OP_ENT(op) OR1K_OPERAND_##op macro 54 { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 }, 68 { INPUT, "rB", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RB), 0, 0 }, 76 { INPUT, "rB", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RB), 0, 0 }, 121 { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 }, 128 { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 }, 129 { INPUT, "rB", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RB), 0, 0 }, 136 { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 }, 144 { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 }, 152 { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 }, [all …]