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Searched refs:PACKET3_BASE_INDEX (Results 1 – 15 of 15) sorted by relevance

/netbsd/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Dsi_enums.h177 #define PACKET3_BASE_INDEX(x) ((x) << 0) macro
H A Dnvd.h59 #define PACKET3_BASE_INDEX(x) ((x) << 0) macro
H A Dsoc15d.h84 #define PACKET3_BASE_INDEX(x) ((x) << 0) macro
H A Dvid.h118 #define PACKET3_BASE_INDEX(x) ((x) << 0) macro
H A Dcikd.h236 #define PACKET3_BASE_INDEX(x) ((x) << 0) macro
H A Dsid.h1669 #define PACKET3_BASE_INDEX(x) ((x) << 0) macro
H A Damdgpu_gfx_v6_0.c2050 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); in gfx_v6_0_cp_gfx_start()
H A Damdgpu_gfx_v7_0.c2553 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); in gfx_v7_0_cp_gfx_start()
H A Damdgpu_gfx_v10_0.c2713 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); in gfx_v10_0_cp_gfx_start()
H A Damdgpu_gfx_v9_0.c3161 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); in gfx_v9_0_cp_gfx_start()
H A Damdgpu_gfx_v8_0.c4224 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); in gfx_v8_0_cp_gfx_start()
/netbsd/sys/external/bsd/drm2/dist/drm/radeon/
H A Dsid.h1606 #define PACKET3_BASE_INDEX(x) ((x) << 0) macro
H A Dcikd.h1702 #define PACKET3_BASE_INDEX(x) ((x) << 0) macro
H A Dradeon_si.c3589 radeon_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); in si_cp_start()
H A Dradeon_cik.c4018 radeon_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); in cik_cp_gfx_start()