Searched refs:PIPECONF (Results 1 – 10 of 10) sorted by relevance
/netbsd/sys/external/bsd/drm2/dist/drm/i915/gvt/ |
H A D | display.c | 67 if (!(vgpu_vreg_t(vgpu, PIPECONF(_PIPE_EDP)) & PIPECONF_ENABLE)) in edp_pipe_is_enabled() 82 if (vgpu_vreg_t(vgpu, PIPECONF(pipe)) & PIPECONF_ENABLE) in pipe_is_enabled() 310 vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_ENABLE; in emulate_monitor_status_change()
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H A D | handlers.c | 1987 MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write); in init_generic_mmio_info() 1988 MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write); in init_generic_mmio_info() 1989 MMIO_DH(PIPECONF(PIPE_C), D_ALL, NULL, pipeconf_mmio_write); in init_generic_mmio_info() 1990 MMIO_DH(PIPECONF(_PIPE_EDP), D_ALL, NULL, pipeconf_mmio_write); in init_generic_mmio_info()
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/netbsd/sys/external/bsd/drm2/dist/drm/i915/display/ |
H A D | icl_dsi.c | 938 tmp = I915_READ(PIPECONF(dsi_trans)); in gen11_dsi_enable_transcoder() 940 I915_WRITE(PIPECONF(dsi_trans), tmp); in gen11_dsi_enable_transcoder() 943 if (intel_de_wait_for_set(dev_priv, PIPECONF(dsi_trans), in gen11_dsi_enable_transcoder() 1121 tmp = I915_READ(PIPECONF(dsi_trans)); in gen11_dsi_disable_transcoder() 1123 I915_WRITE(PIPECONF(dsi_trans), tmp); in gen11_dsi_disable_transcoder() 1126 if (intel_de_wait_for_clear(dev_priv, PIPECONF(dsi_trans), in gen11_dsi_disable_transcoder() 1470 tmp = I915_READ(PIPECONF(dsi_trans)); in gen11_dsi_get_hw_state()
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H A D | intel_color.c | 453 val = I915_READ(PIPECONF(pipe)); in i9xx_color_commit() 456 I915_WRITE(PIPECONF(pipe), val); in i9xx_color_commit() 466 val = I915_READ(PIPECONF(pipe)); in ilk_color_commit() 469 I915_WRITE(PIPECONF(pipe), val); in ilk_color_commit()
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H A D | intel_display.c | 1674 pipeconf_val = I915_READ(PIPECONF(pipe)); in ilk_enable_pch_transcoder() 1873 reg = PIPECONF(cpu_transcoder); in intel_enable_pipe() 1914 reg = PIPECONF(cpu_transcoder); in intel_disable_pipe() 8830 POSTING_READ(PIPECONF(crtc->pipe)); in i9xx_set_pipeconf() 9259 tmp = I915_READ(PIPECONF(crtc->pipe)); in i9xx_get_pipe_config() 9912 I915_WRITE(PIPECONF(pipe), val); in ilk_set_pipeconf() 9913 POSTING_READ(PIPECONF(pipe)); in ilk_set_pipeconf() 10455 tmp = I915_READ(PIPECONF(crtc->pipe)); in ilk_get_pipe_config() 17757 POSTING_READ(PIPECONF(pipe)); in i830_enable_pipe() 17775 I915_WRITE(PIPECONF(pipe), 0); in i830_disable_pipe() [all …]
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H A D | intel_crt.c | 674 pipeconf_reg = PIPECONF(pipe); in intel_crt_load_detect()
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H A D | intel_display_power.c | 1120 if ((I915_READ(PIPECONF(PIPE_A)) & PIPECONF_ENABLE) == 0) in i830_pipes_power_well_enable() 1122 if ((I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE) == 0) in i830_pipes_power_well_enable() 1136 return I915_READ(PIPECONF(PIPE_A)) & PIPECONF_ENABLE && in i830_pipes_power_well_enabled() 1137 I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE; in i830_pipes_power_well_enabled()
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H A D | vlv_dsi.c | 996 enabled = I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE; in intel_dsi_get_hw_state()
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H A D | intel_dp.c | 7050 i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder); in intel_dp_set_drrs_state()
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/netbsd/sys/external/bsd/drm2/dist/drm/i915/ |
H A D | i915_reg.h | 5871 #define PIPECONF(pipe) _MMIO_PIPE2(pipe, _PIPEACONF) macro
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