| /netbsd/tests/usr.bin/xlint/lint1/ |
| H A D | queries.c | 394 Q12(void) in Q12() function
|
| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64PBQPRegAlloc.cpp | 134 case AArch64::Q12: in isOdd()
|
| H A D | AArch64SchedPredicates.td | 182 CheckRegOperand<0, Q12>,
|
| H A D | AArch64RegisterInfo.td | 403 def Q12 : AArch64Reg<12, "q12", [D12], ["v12", ""]>, DwarfRegAlias<B12>;
807 def Z12 : AArch64Reg<12, "z12", [Q12, Z12_HI]>, DwarfRegNum<[108]>;
|
| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMMCTargetDesc.cpp | 318 {codeview::RegisterId::ARM_NQ12, ARM::Q12}, in initLLVMToCVRegMapping()
|
| H A D | ARMMCCodeEmitter.cpp | 574 case ARM::Q12: case ARM::Q13: case ARM::Q14: case ARM::Q15: in getMachineOpValue()
|
| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64MCTargetDesc.cpp | 211 {codeview::RegisterId::ARM64_Q12, AArch64::Q12}, in initLLVMToCVRegMapping()
|
| H A D | AArch64InstPrinter.cpp | 1190 case AArch64::Q11: Reg = AArch64::Q12; break; in getNextVectorRegister()
1191 case AArch64::Q12: Reg = AArch64::Q13; break; in getNextVectorRegister()
|
| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/Sparc/Disassembler/ |
| H A D | SparcDisassembler.cpp | 95 SP::Q4, SP::Q12, ~0U, ~0U,
|
| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/Sparc/ |
| H A D | SparcRegisterInfo.td | 280 def Q12 : Rq<17, "F48", [D24, D25]>;
|
| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/VE/Disassembler/ |
| H A D | VEDisassembler.cpp | 94 VE::Q8, VE::Q9, VE::Q10, VE::Q11, VE::Q12, VE::Q13, VE::Q14, VE::Q15,
|
| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/AArch64/Disassembler/ |
| H A D | AArch64Disassembler.cpp | 322 AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14,
675 AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14,
|
| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/Sparc/AsmParser/ |
| H A D | SparcAsmParser.cpp | 169 Sparc::Q12, Sparc::Q13, Sparc::Q14, Sparc::Q15 };
|
| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/VE/AsmParser/ |
| H A D | VEAsmParser.cpp | 124 VE::Q8, VE::Q9, VE::Q10, VE::Q11, VE::Q12, VE::Q13, VE::Q14, VE::Q15,
|
| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMRegisterInfo.td | 171 def Q12 : ARMReg<12, "q12", [D24, D25]>;
|
| H A D | ARMInstrThumb2.td | 3813 Q0, Q1, Q2, Q3, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15],
|
| H A D | ARMInstrInfo.td | 5873 Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 ],
|
| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/ARM/Disassembler/ |
| H A D | ARMDisassembler.cpp | 1388 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
1407 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
|
| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 2171 .Case("v12", AArch64::Q12) in MatchNeonVectorRegName()
|