/netbsd/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/Disassembler/ |
H A D | HexagonDisassembler.cpp | 212 MI.getOperand(1).getReg() == Hexagon::R30) { in remapInstruction() 220 MI.getOperand(1).getReg() == Hexagon::R30) { in remapInstruction() 228 MI.getOperand(2).getReg() == Hexagon::R30) { in remapInstruction() 236 MI.getOperand(2).getReg() == Hexagon::R30) { in remapInstruction() 244 MI.getOperand(2).getReg() == Hexagon::R30) { in remapInstruction() 252 MI.getOperand(2).getReg() == Hexagon::R30) { in remapInstruction() 260 MI.getOperand(2).getReg() == Hexagon::R30) { in remapInstruction() 268 MI.getOperand(2).getReg() == Hexagon::R30) { in remapInstruction() 554 Hexagon::R30, Hexagon::R31}; in DecodeIntRegsRegisterClass()
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/netbsd/external/bsd/pcc/dist/pcc/arch/powerpc/ |
H A D | macdefs.h | 177 #define R30 30 macro 327 { R30, R31, -1 }, \ 341 #define FPREG R30 /* frame pointer */
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H A D | order.c | 385 static int r[] = { R10, R9, R8, R7, R6, R5, R4, R3, R30, R31, -1 }; in livecall()
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H A D | local2.c | 131 printf("\tstmw %s,-8(%s)\n", rnames[R30], rnames[R1]); in prologue() 182 printf("\tlmw %s,-8(%s)\n", rnames[R30], rnames[R1]); in eoftn()
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
H A D | HexagonPseudo.td | 81 let Defs = [R29, R30], Uses = [R31, R30, R29], isPseudo = 1 in 85 let Defs = [R29, R30, R31], Uses = [R29], isPseudo = 1 in 248 let isCodeGenOnly = 1, isPseudo = 1, Uses = [R30], hasSideEffects = 0 in 353 Defs = [R29, R30, R31, PC], isPredicable = 0, isAsmParserOnly = 1 in { 359 let Defs = [R14, R15, R28, R29, R30, R31, PC] in { 368 let isCall = 1, Defs = [R29, R30, R31, PC], isAsmParserOnly = 1 in { 374 let Defs = [R14, R15, R28, R29, R30, R31, PC] in {
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H A D | HexagonRegisterInfo.cpp | 151 Reserved.set(Hexagon::R30); in getReservedRegs() 411 return Hexagon::R30; in getFrameRegister()
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H A D | HexagonRegisterInfo.td | 107 def R30 : Ri<30, "r30", ["fp"]>, DwarfRegNum<[30]>; 127 def D15 : Rd<30, "r31:30", [R30, R31], ["lr:fp"]>, DwarfRegNum<[62]>; 374 R10, R11, R29, R30, R31)>;
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H A D | HexagonDepMappings.td | 85 …_map_to_raw_fAlias : InstAlias<"if (!$Pv4) dealloc_return", (L4_return_f D15, PredRegs:$Pv4, R30)>; 86 …lias : InstAlias<"if (!$Pv4.new) dealloc_return:nt", (L4_return_fnew_pnt D15, PredRegs:$Pv4, R30)>; 87 …tAlias : InstAlias<"if (!$Pv4.new) dealloc_return:t", (L4_return_fnew_pt D15, PredRegs:$Pv4, R30)>; 88 …n_map_to_raw_tAlias : InstAlias<"if ($Pv4) dealloc_return", (L4_return_t D15, PredRegs:$Pv4, R30)>; 89 …Alias : InstAlias<"if ($Pv4.new) dealloc_return:nt", (L4_return_tnew_pnt D15, PredRegs:$Pv4, R30)>; 90 …ptAlias : InstAlias<"if ($Pv4.new) dealloc_return:t", (L4_return_tnew_pt D15, PredRegs:$Pv4, R30)>; 94 def L6_deallocframe_map_to_rawAlias : InstAlias<"deallocframe", (L2_deallocframe D15, R30)>; 95 def L6_return_map_to_rawAlias : InstAlias<"dealloc_return", (L4_return D15, R30)>;
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/ARC/ |
H A D | ARCRegisterInfo.td | 62 def R30 : Core<30, "%r30">, DwarfRegNum<[30]>; 73 R20, R21, R22, R23, R24, R25, GP, FP, SP, ILINK, R30, BLINK)>;
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/AVR/ |
H A D | AVRRegisterInfo.td | 74 def R30 : AVRReg<30, "r30", [], ["zl"]>, DwarfRegNum<[30]>; 89 def R31R30 : AVRReg<30, "r31:r30", [R30, R31], ["Z"]>, DwarfRegNum<[30]>; 129 R30, R31, R26, R27, 147 R30, R31, R26, R27,
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/netbsd/external/gpl3/gcc/dist/gcc/config/pru/ |
H A D | constraints.md | 37 ;; Rrio: The R30 and R31 I/O registers. 63 The R30 and R31 I/O registers.")
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H A D | pru.md | 39 (R30_REGNUM 120) ; R30 I/O register. 57 (ADDR_SPACE_REGIO 1) ; Access to R30 and R31 I/O registers. 612 ;; Patterns for accessing the R30/R31 I/O registers.
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/netbsd/external/gpl3/gdb/dist/sim/aarch64/ |
H A D | cpustate.h | 72 R30, enumerator 75 LR = R30,
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/netbsd/external/gpl3/gdb.old/dist/sim/aarch64/ |
H A D | cpustate.h | 72 R30, enumerator 75 LR = R30,
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/Lanai/MCTargetDesc/ |
H A D | LanaiBaseInfo.h | 109 case Lanai::R30: in getLanaiRegisterNumbering()
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/netbsd/external/gpl3/gcc.old/dist/libgcc/config/avr/libf7/ |
H A D | asm-defs.h | 124 R30, R31
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/netbsd/external/gpl3/gcc/dist/libgcc/config/avr/libf7/ |
H A D | asm-defs.h | 124 R30, R31
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
H A D | PPCFrameLowering.cpp | 120 {PPC::R30, -8}, \ in getCalleeSavedSpillSlots() 830 .addReg(PPC::R30) in emitPrologue() 1024 .addReg(PPC::R30, RegState::Kill) // Save PIC base pointer. in emitPrologue() 1056 .addReg(PPC::R30) in emitPrologue() 1081 .addReg(PPC::R30) in emitPrologue() 1127 unsigned Reg = MRI->getDwarfRegNum(PPC::R30, true); in emitPrologue() 1812 BuildMI(MBB, MBBI, dl, LoadInst, PPC::R30) in emitEpilogue() 2013 SavedRegs.reset(PPC::R30); in determineCalleeSaves() 2166 MinGPR = std::min<unsigned>(MinGPR, PPC::R30); in processFunctionBeforeFrameFinalized()
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H A D | PPCCallingConv.td | 273 R28, R29, R30, R31, CR2, CR3, CR4 289 R29, R30, R31, F14, F15, F16, F17, F18,
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H A D | PPCRegisterInfo.cpp | 340 markSuperRegs(Reserved, PPC::R30); in getReservedRegs() 344 markSuperRegs(Reserved, PPC::R30); in getReservedRegs() 1383 return PPC::R30; in getBaseRegister()
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/Lanai/Disassembler/ |
H A D | LanaiDisassembler.cpp | 161 Lanai::R30, Lanai::R31};
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/AVR/Disassembler/ |
H A D | AVRDisassembler.cpp | 68 AVR::R28, AVR::R29, AVR::R30, AVR::R31,
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/ARC/Disassembler/ |
H A D | ARCDisassembler.cpp | 118 ARC::SP, ARC::ILINK, ARC::R30, ARC::BLINK};
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/CSKY/ |
H A D | CSKYRegisterInfo.td | 82 def R30 : CSKYReg<30, "r30", ["svbr"]>, DwarfRegNum<[30]>;
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/netbsd/sys/external/bsd/gnu-efi/dist/inc/ |
H A D | efidebug.h | 358 UINT64 R30; member
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