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Searched refs:RADEON_CLOCK_CNTL_INDEX (Results 1 – 10 of 10) sorted by relevance

/netbsd/sys/dev/pci/
H A Dradeonfb.c1568 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); in radeonfb_putpll()
1636 PRINTREG(RADEON_CLOCK_CNTL_INDEX); in radeonfb_getclocks()
2183 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, 0, in radeonfb_program_vclk()
2203 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, 0, in radeonfb_program_vclk()
2542 PRINTREG(RADEON_CLOCK_CNTL_INDEX); in radeonfb_setcrtc()
3044 save = GET32(sc, RADEON_CLOCK_CNTL_INDEX); in radeonfb_r300cg_workaround()
3046 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, tmp); in radeonfb_r300cg_workaround()
3048 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, save); in radeonfb_r300cg_workaround()
3770 clkindex = GET32(sc, RADEON_CLOCK_CNTL_INDEX); in radeonfb_engine_reset()
3821 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, clkindex); in radeonfb_engine_reset()
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H A Dradeonfbreg.h330 #define RADEON_CLOCK_CNTL_INDEX 0x0008 macro
/netbsd/sys/external/bsd/drm2/dist/drm/radeon/
H A Dradeon_legacy_crtc.c953 WREG32_P(RADEON_CLOCK_CNTL_INDEX, in radeon_set_pll()
974 WREG32_P(RADEON_CLOCK_CNTL_INDEX, in radeon_set_pll()
H A Dradeon_r100.c2891 save = RREG32(RADEON_CLOCK_CNTL_INDEX); in r100_pll_errata_after_data()
2893 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp); in r100_pll_errata_after_data()
2895 WREG32(RADEON_CLOCK_CNTL_INDEX, save); in r100_pll_errata_after_data()
2905 WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f); in r100_pll_rreg()
2918 WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN)); in r100_pll_wreg()
H A Dradeon_legacy_tv.c294 WREG8(RADEON_CLOCK_CNTL_INDEX, RADEON_PLL_TEST_CNTL); in radeon_wait_pll_lock()
H A Dradeon_legacy_encoders.c250 WREG32(RADEON_CLOCK_CNTL_INDEX, 0); in radeon_legacy_lvds_mode_set()
H A Dradeon_reg.h348 #define RADEON_CLOCK_CNTL_INDEX 0x0008 macro
H A Dradeon_combios.c1155 ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3; in radeon_legacy_get_lvds_info_from_regs()
/netbsd/sys/external/bsd/drm/dist/shared-core/
H A Dradeon_cp.c207 RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f); in RADEON_READ_PLL()
555 clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX); in radeon_do_engine_reset()
590 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index); in radeon_do_engine_reset()
H A Dradeon_drv.h608 #define RADEON_CLOCK_CNTL_INDEX 0x0008 macro
1877 RADEON_WRITE8( RADEON_CLOCK_CNTL_INDEX, \