Home
last modified time | relevance | path

Searched refs:RADEON_MCLK_CNTL (Results 1 – 8 of 8) sorted by relevance

/netbsd/sys/external/bsd/drm2/dist/drm/radeon/
H A Dradeon_clocks.c93 post_div = RREG32_PLL(RADEON_MCLK_CNTL) & 0x7; in radeon_legacy_get_memory_clock()
610 tmp = RREG32_PLL(RADEON_MCLK_CNTL); in radeon_legacy_set_clock_gating()
625 tmp = RREG32_PLL(RADEON_MCLK_CNTL); in radeon_legacy_set_clock_gating()
640 WREG32_PLL(RADEON_MCLK_CNTL, tmp); in radeon_legacy_set_clock_gating()
817 tmp = RREG32_PLL(RADEON_MCLK_CNTL); in radeon_legacy_set_clock_gating()
822 WREG32_PLL(RADEON_MCLK_CNTL, tmp); in radeon_legacy_set_clock_gating()
887 tmp = RREG32_PLL(RADEON_MCLK_CNTL); in radeon_legacy_set_clock_gating()
890 WREG32_PLL(RADEON_MCLK_CNTL, tmp); in radeon_legacy_set_clock_gating()
H A Dradeon_combios.c3164 (RADEON_MCLK_CNTL); in combios_parse_pll_table()
3167 WREG32_PLL(RADEON_MCLK_CNTL, in combios_parse_pll_table()
H A Dradeon_reg.h1177 #define RADEON_MCLK_CNTL 0x0012 /* PLL */ macro
/netbsd/sys/dev/pci/
H A Dradeonfb_bios.c346 radeonfb_maskpll(sc, RADEON_MCLK_CNTL, 0xFFFF0000, in rb_wait_chk_set_clk_pwrmgt_cntl24()
H A Dradeonfb.c3773 mclkcntl = GETPLL(sc, RADEON_MCLK_CNTL); in radeonfb_engine_reset()
3823 PUTPLL(sc, RADEON_MCLK_CNTL, mclkcntl); in radeonfb_engine_reset()
H A Dradeonfbreg.h1127 #define RADEON_MCLK_CNTL 0x0012 /* PLL */ macro
/netbsd/sys/external/bsd/drm/dist/shared-core/
H A Dradeon_cp.c556 mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL); in radeon_do_engine_reset()
558 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl | in radeon_do_engine_reset()
589 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl); in radeon_do_engine_reset()
H A Dradeon_drv.h890 #define RADEON_MCLK_CNTL 0x0012 macro