1 /* $NetBSD: radeon.h,v 1.11 2021/12/19 11:52:38 riastradh Exp $ */
2
3 /*
4 * Copyright 2008 Advanced Micro Devices, Inc.
5 * Copyright 2008 Red Hat Inc.
6 * Copyright 2009 Jerome Glisse.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
24 * OTHER DEALINGS IN THE SOFTWARE.
25 *
26 * Authors: Dave Airlie
27 * Alex Deucher
28 * Jerome Glisse
29 */
30 #ifndef __RADEON_H__
31 #define __RADEON_H__
32
33 /* TODO: Here are things that needs to be done :
34 * - surface allocator & initializer : (bit like scratch reg) should
35 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
36 * related to surface
37 * - WB : write back stuff (do it bit like scratch reg things)
38 * - Vblank : look at Jesse's rework and what we should do
39 * - r600/r700: gart & cp
40 * - cs : clean cs ioctl use bitmap & things like that.
41 * - power management stuff
42 * - Barrier in gart code
43 * - Unmappabled vram ?
44 * - TESTING, TESTING, TESTING
45 */
46
47 /* Initialization path:
48 * We expect that acceleration initialization might fail for various
49 * reasons even thought we work hard to make it works on most
50 * configurations. In order to still have a working userspace in such
51 * situation the init path must succeed up to the memory controller
52 * initialization point. Failure before this point are considered as
53 * fatal error. Here is the init callchain :
54 * radeon_device_init perform common structure, mutex initialization
55 * asic_init setup the GPU memory layout and perform all
56 * one time initialization (failure in this
57 * function are considered fatal)
58 * asic_startup setup the GPU acceleration, in order to
59 * follow guideline the first thing this
60 * function should do is setting the GPU
61 * memory controller (only MC setup failure
62 * are considered as fatal)
63 */
64
65 #include <linux/atomic.h>
66 #include <linux/wait.h>
67 #include <linux/list.h>
68 #include <linux/kref.h>
69 #include <linux/interval_tree.h>
70 #include <linux/hashtable.h>
71 #include <linux/dma-fence.h>
72
73 #ifdef CONFIG_MMU_NOTIFIER
74 #include <linux/mmu_notifier.h>
75 #endif
76
77 #include <drm/ttm/ttm_bo_api.h>
78 #include <drm/ttm/ttm_bo_driver.h>
79 #include <drm/ttm/ttm_placement.h>
80 #include <drm/ttm/ttm_module.h>
81 #include <drm/ttm/ttm_execbuf_util.h>
82
83 #include <drm/drm_gem.h>
84
85 #include "radeon_family.h"
86 #include "radeon_mode.h"
87 #include "radeon_reg.h"
88
89 /*
90 * Modules parameters.
91 */
92 extern int radeon_no_wb;
93 extern int radeon_modeset;
94 extern int radeon_dynclks;
95 extern int radeon_r4xx_atom;
96 extern int radeon_agpmode;
97 extern int radeon_vram_limit;
98 extern int radeon_gart_size;
99 extern int radeon_benchmarking;
100 extern int radeon_testing;
101 extern int radeon_connector_table;
102 extern int radeon_tv;
103 extern int radeon_audio;
104 extern int radeon_disp_priority;
105 extern int radeon_hw_i2c;
106 extern int radeon_pcie_gen2;
107 extern int radeon_msi;
108 extern int radeon_lockup_timeout;
109 extern int radeon_fastfb;
110 extern int radeon_dpm;
111 extern int radeon_aspm;
112 extern int radeon_runtime_pm;
113 extern int radeon_hard_reset;
114 extern int radeon_vm_size;
115 extern int radeon_vm_block_size;
116 extern int radeon_deep_color;
117 extern int radeon_use_pflipirq;
118 extern int radeon_bapm;
119 extern int radeon_backlight;
120 extern int radeon_auxch;
121 extern int radeon_mst;
122 extern int radeon_uvd;
123 extern int radeon_vce;
124 extern int radeon_si_support;
125 extern int radeon_cik_support;
126
127 /*
128 * Copy from radeon_drv.h so we don't have to include both and have conflicting
129 * symbol;
130 */
131 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
132 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
133 #define RADEON_USEC_IB_TEST_TIMEOUT 1000000 /* 1s */
134 /* RADEON_IB_POOL_SIZE must be a power of 2 */
135 #define RADEON_IB_POOL_SIZE 16
136 #define RADEON_DEBUGFS_MAX_COMPONENTS 32
137 #define RADEONFB_CONN_LIMIT 4
138 #define RADEON_BIOS_NUM_SCRATCH 8
139
140 /* internal ring indices */
141 /* r1xx+ has gfx CP ring */
142 #define RADEON_RING_TYPE_GFX_INDEX 0
143
144 /* cayman has 2 compute CP rings */
145 #define CAYMAN_RING_TYPE_CP1_INDEX 1
146 #define CAYMAN_RING_TYPE_CP2_INDEX 2
147
148 /* R600+ has an async dma ring */
149 #define R600_RING_TYPE_DMA_INDEX 3
150 /* cayman add a second async dma ring */
151 #define CAYMAN_RING_TYPE_DMA1_INDEX 4
152
153 /* R600+ */
154 #define R600_RING_TYPE_UVD_INDEX 5
155
156 /* TN+ */
157 #define TN_RING_TYPE_VCE1_INDEX 6
158 #define TN_RING_TYPE_VCE2_INDEX 7
159
160 /* max number of rings */
161 #define RADEON_NUM_RINGS 8
162
163 /* number of hw syncs before falling back on blocking */
164 #define RADEON_NUM_SYNCS 4
165
166 /* hardcode those limit for now */
167 #define RADEON_VA_IB_OFFSET (1 << 20)
168 #define RADEON_VA_RESERVED_SIZE (8 << 20)
169 #define RADEON_IB_VM_MAX_SIZE (64 << 10)
170
171 /* hard reset data */
172 #define RADEON_ASIC_RESET_DATA 0x39d5e86b
173
174 /* reset flags */
175 #define RADEON_RESET_GFX (1 << 0)
176 #define RADEON_RESET_COMPUTE (1 << 1)
177 #define RADEON_RESET_DMA (1 << 2)
178 #define RADEON_RESET_CP (1 << 3)
179 #define RADEON_RESET_GRBM (1 << 4)
180 #define RADEON_RESET_DMA1 (1 << 5)
181 #define RADEON_RESET_RLC (1 << 6)
182 #define RADEON_RESET_SEM (1 << 7)
183 #define RADEON_RESET_IH (1 << 8)
184 #define RADEON_RESET_VMC (1 << 9)
185 #define RADEON_RESET_MC (1 << 10)
186 #define RADEON_RESET_DISPLAY (1 << 11)
187
188 /* CG block flags */
189 #define RADEON_CG_BLOCK_GFX (1 << 0)
190 #define RADEON_CG_BLOCK_MC (1 << 1)
191 #define RADEON_CG_BLOCK_SDMA (1 << 2)
192 #define RADEON_CG_BLOCK_UVD (1 << 3)
193 #define RADEON_CG_BLOCK_VCE (1 << 4)
194 #define RADEON_CG_BLOCK_HDP (1 << 5)
195 #define RADEON_CG_BLOCK_BIF (1 << 6)
196
197 /* CG flags */
198 #define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0)
199 #define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1)
200 #define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2)
201 #define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3)
202 #define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4)
203 #define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
204 #define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6)
205 #define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7)
206 #define RADEON_CG_SUPPORT_MC_LS (1 << 8)
207 #define RADEON_CG_SUPPORT_MC_MGCG (1 << 9)
208 #define RADEON_CG_SUPPORT_SDMA_LS (1 << 10)
209 #define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11)
210 #define RADEON_CG_SUPPORT_BIF_LS (1 << 12)
211 #define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13)
212 #define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14)
213 #define RADEON_CG_SUPPORT_HDP_LS (1 << 15)
214 #define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16)
215
216 /* PG flags */
217 #define RADEON_PG_SUPPORT_GFX_PG (1 << 0)
218 #define RADEON_PG_SUPPORT_GFX_SMG (1 << 1)
219 #define RADEON_PG_SUPPORT_GFX_DMG (1 << 2)
220 #define RADEON_PG_SUPPORT_UVD (1 << 3)
221 #define RADEON_PG_SUPPORT_VCE (1 << 4)
222 #define RADEON_PG_SUPPORT_CP (1 << 5)
223 #define RADEON_PG_SUPPORT_GDS (1 << 6)
224 #define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7)
225 #define RADEON_PG_SUPPORT_SDMA (1 << 8)
226 #define RADEON_PG_SUPPORT_ACP (1 << 9)
227 #define RADEON_PG_SUPPORT_SAMU (1 << 10)
228
229 /* max cursor sizes (in pixels) */
230 #define CURSOR_WIDTH 64
231 #define CURSOR_HEIGHT 64
232
233 #define CIK_CURSOR_WIDTH 128
234 #define CIK_CURSOR_HEIGHT 128
235
236 /*
237 * Errata workarounds.
238 */
239 enum radeon_pll_errata {
240 CHIP_ERRATA_R300_CG = 0x00000001,
241 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
242 CHIP_ERRATA_PLL_DELAY = 0x00000004
243 };
244
245
246 struct radeon_device;
247
248 #ifdef __NetBSD__
249 extern struct radeon_device *radeon_device_private(device_t);
250 #endif
251
252 /*
253 * BIOS.
254 */
255 bool radeon_get_bios(struct radeon_device *rdev);
256
257 /*
258 * Dummy page
259 */
260 struct radeon_dummy_page {
261 uint64_t entry;
262 #ifdef __NetBSD__
263 bus_dma_segment_t rdp_seg;
264 bus_dmamap_t rdp_map;
265 void *rdp_addr;
266 #else
267 struct page *page;
268 #endif
269 dma_addr_t addr;
270 };
271 int radeon_dummy_page_init(struct radeon_device *rdev);
272 void radeon_dummy_page_fini(struct radeon_device *rdev);
273
274
275 /*
276 * Clocks
277 */
278 struct radeon_clock {
279 struct radeon_pll p1pll;
280 struct radeon_pll p2pll;
281 struct radeon_pll dcpll;
282 struct radeon_pll spll;
283 struct radeon_pll mpll;
284 /* 10 Khz units */
285 uint32_t default_mclk;
286 uint32_t default_sclk;
287 uint32_t default_dispclk;
288 uint32_t current_dispclk;
289 uint32_t dp_extclk;
290 uint32_t max_pixel_clock;
291 uint32_t vco_freq;
292 };
293
294 /*
295 * Power management
296 */
297 int radeon_pm_init(struct radeon_device *rdev);
298 int radeon_pm_late_init(struct radeon_device *rdev);
299 void radeon_pm_fini(struct radeon_device *rdev);
300 void radeon_pm_compute_clocks(struct radeon_device *rdev);
301 void radeon_pm_suspend(struct radeon_device *rdev);
302 void radeon_pm_resume(struct radeon_device *rdev);
303 void radeon_combios_get_power_modes(struct radeon_device *rdev);
304 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
305 int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
306 u8 clock_type,
307 u32 clock,
308 bool strobe_mode,
309 struct atom_clock_dividers *dividers);
310 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
311 u32 clock,
312 bool strobe_mode,
313 struct atom_mpll_param *mpll_param);
314 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
315 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
316 u16 voltage_level, u8 voltage_type,
317 u32 *gpio_value, u32 *gpio_mask);
318 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
319 u32 eng_clock, u32 mem_clock);
320 int radeon_atom_get_voltage_step(struct radeon_device *rdev,
321 u8 voltage_type, u16 *voltage_step);
322 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
323 u16 voltage_id, u16 *voltage);
324 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
325 u16 *voltage,
326 u16 leakage_idx);
327 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
328 u16 *leakage_id);
329 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
330 u16 *vddc, u16 *vddci,
331 u16 virtual_voltage_id,
332 u16 vbios_voltage_id);
333 int radeon_atom_get_voltage_evv(struct radeon_device *rdev,
334 u16 virtual_voltage_id,
335 u16 *voltage);
336 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
337 u8 voltage_type,
338 u16 nominal_voltage,
339 u16 *true_voltage);
340 int radeon_atom_get_min_voltage(struct radeon_device *rdev,
341 u8 voltage_type, u16 *min_voltage);
342 int radeon_atom_get_max_voltage(struct radeon_device *rdev,
343 u8 voltage_type, u16 *max_voltage);
344 int radeon_atom_get_voltage_table(struct radeon_device *rdev,
345 u8 voltage_type, u8 voltage_mode,
346 struct atom_voltage_table *voltage_table);
347 bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
348 u8 voltage_type, u8 voltage_mode);
349 int radeon_atom_get_svi2_info(struct radeon_device *rdev,
350 u8 voltage_type,
351 u8 *svd_gpio_id, u8 *svc_gpio_id);
352 void radeon_atom_update_memory_dll(struct radeon_device *rdev,
353 u32 mem_clock);
354 void radeon_atom_set_ac_timing(struct radeon_device *rdev,
355 u32 mem_clock);
356 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
357 u8 module_index,
358 struct atom_mc_reg_table *reg_table);
359 int radeon_atom_get_memory_info(struct radeon_device *rdev,
360 u8 module_index, struct atom_memory_info *mem_info);
361 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
362 bool gddr5, u8 module_index,
363 struct atom_memory_clock_range_table *mclk_range_table);
364 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
365 u16 voltage_id, u16 *voltage);
366 void rs690_pm_info(struct radeon_device *rdev);
367 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
368 unsigned *bankh, unsigned *mtaspect,
369 unsigned *tile_split);
370
371 /*
372 * Fences.
373 */
374 struct radeon_fence_driver {
375 struct radeon_device *rdev;
376 uint32_t scratch_reg;
377 uint64_t gpu_addr;
378 volatile uint32_t *cpu_addr;
379 /* sync_seq is protected by ring emission lock */
380 uint64_t sync_seq[RADEON_NUM_RINGS];
381 atomic64_t last_seq;
382 bool initialized, delayed_irq;
383 struct delayed_work lockup_work;
384 };
385
386 struct radeon_fence {
387 struct dma_fence base;
388
389 struct radeon_device *rdev;
390 uint64_t seq;
391 /* RB, DMA, etc. */
392 unsigned ring;
393 bool is_vm_update;
394
395 TAILQ_ENTRY(radeon_fence) fence_check;
396 };
397
398 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
399 int radeon_fence_driver_init(struct radeon_device *rdev);
400 void radeon_fence_driver_fini(struct radeon_device *rdev);
401 void radeon_fence_driver_force_completion(struct radeon_device *rdev, int ring);
402 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
403 void radeon_fence_wakeup_locked(struct radeon_device *rdev);
404 void radeon_fence_process(struct radeon_device *rdev, int ring);
405 bool radeon_fence_signaled(struct radeon_fence *fence);
406 long radeon_fence_wait_timeout(struct radeon_fence *fence, bool interruptible, long timeout);
407 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
408 int radeon_fence_wait_next(struct radeon_device *rdev, int ring);
409 int radeon_fence_wait_empty(struct radeon_device *rdev, int ring);
410 int radeon_fence_wait_any(struct radeon_device *rdev,
411 struct radeon_fence **fences,
412 bool intr);
413 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
414 void radeon_fence_unref(struct radeon_fence **fence);
415 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
416 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
417 void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
radeon_fence_later(struct radeon_fence * a,struct radeon_fence * b)418 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
419 struct radeon_fence *b)
420 {
421 if (!a) {
422 return b;
423 }
424
425 if (!b) {
426 return a;
427 }
428
429 BUG_ON(a->ring != b->ring);
430
431 if (a->seq > b->seq) {
432 return a;
433 } else {
434 return b;
435 }
436 }
437
radeon_fence_is_earlier(struct radeon_fence * a,struct radeon_fence * b)438 static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
439 struct radeon_fence *b)
440 {
441 if (!a) {
442 return false;
443 }
444
445 if (!b) {
446 return true;
447 }
448
449 BUG_ON(a->ring != b->ring);
450
451 return a->seq < b->seq;
452 }
453
454 /*
455 * Tiling registers
456 */
457 struct radeon_surface_reg {
458 struct radeon_bo *bo;
459 };
460
461 #define RADEON_GEM_MAX_SURFACES 8
462
463 /*
464 * TTM.
465 */
466 struct radeon_mman {
467 struct ttm_bo_device bdev;
468 bool initialized;
469
470 #if defined(CONFIG_DEBUG_FS)
471 struct dentry *vram;
472 struct dentry *gtt;
473 #endif
474 };
475
476 struct radeon_bo_list {
477 struct radeon_bo *robj;
478 struct ttm_validate_buffer tv;
479 uint64_t gpu_offset;
480 unsigned preferred_domains;
481 unsigned allowed_domains;
482 uint32_t tiling_flags;
483 };
484
485 /* bo virtual address in a specific vm */
486 struct radeon_bo_va {
487 /* protected by bo being reserved */
488 struct list_head bo_list;
489 uint32_t flags;
490 struct radeon_fence *last_pt_update;
491 unsigned ref_count;
492
493 /* protected by vm mutex */
494 struct interval_tree_node it;
495 struct list_head vm_status;
496
497 /* constant after initialization */
498 struct radeon_vm *vm;
499 struct radeon_bo *bo;
500 };
501
502 struct radeon_bo {
503 /* Protected by gem.mutex */
504 struct list_head list;
505 /* Protected by tbo.reserved */
506 u32 initial_domain;
507 struct ttm_place placements[4];
508 struct ttm_placement placement;
509 struct ttm_buffer_object tbo;
510 struct ttm_bo_kmap_obj kmap;
511 u32 flags;
512 unsigned pin_count;
513 void *kptr;
514 u32 tiling_flags;
515 u32 pitch;
516 int surface_reg;
517 unsigned prime_shared_count;
518 /* list of all virtual address to which this bo
519 * is associated to
520 */
521 struct list_head va;
522 /* Constant after initialization */
523 struct radeon_device *rdev;
524
525 struct ttm_bo_kmap_obj dma_buf_vmap;
526 #ifndef __NetBSD__ /* XXX pid??? */
527 pid_t pid;
528 #endif
529
530 #ifdef CONFIG_MMU_NOTIFIER
531 struct mmu_interval_notifier notifier;
532 #endif
533 };
534 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, tbo.base)
535
536 int radeon_gem_debugfs_init(struct radeon_device *rdev);
537
538 /* sub-allocation manager, it has to be protected by another lock.
539 * By conception this is an helper for other part of the driver
540 * like the indirect buffer or semaphore, which both have their
541 * locking.
542 *
543 * Principe is simple, we keep a list of sub allocation in offset
544 * order (first entry has offset == 0, last entry has the highest
545 * offset).
546 *
547 * When allocating new object we first check if there is room at
548 * the end total_size - (last_object_offset + last_object_size) >=
549 * alloc_size. If so we allocate new object there.
550 *
551 * When there is not enough room at the end, we start waiting for
552 * each sub object until we reach object_offset+object_size >=
553 * alloc_size, this object then become the sub object we return.
554 *
555 * Alignment can't be bigger than page size.
556 *
557 * Hole are not considered for allocation to keep things simple.
558 * Assumption is that there won't be hole (all object on same
559 * alignment).
560 */
561 struct radeon_sa_manager {
562 #ifdef __NetBSD__
563 spinlock_t wq_lock;
564 drm_waitqueue_t wq;
565 #else
566 wait_queue_head_t wq;
567 #endif
568 struct radeon_bo *bo;
569 struct list_head *hole;
570 struct list_head flist[RADEON_NUM_RINGS];
571 struct list_head olist;
572 unsigned size;
573 uint64_t gpu_addr;
574 void *cpu_ptr;
575 uint32_t domain;
576 uint32_t align;
577 };
578
579 struct radeon_sa_bo;
580
581 /* sub-allocation buffer */
582 struct radeon_sa_bo {
583 struct list_head olist;
584 struct list_head flist;
585 struct radeon_sa_manager *manager;
586 unsigned soffset;
587 unsigned eoffset;
588 struct radeon_fence *fence;
589 };
590
591 /*
592 * GEM objects.
593 */
594 struct radeon_gem {
595 struct mutex mutex;
596 struct list_head objects;
597 };
598
599 int radeon_gem_init(struct radeon_device *rdev);
600 void radeon_gem_fini(struct radeon_device *rdev);
601 int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size,
602 int alignment, int initial_domain,
603 u32 flags, bool kernel,
604 struct drm_gem_object **obj);
605
606 int radeon_mode_dumb_create(struct drm_file *file_priv,
607 struct drm_device *dev,
608 struct drm_mode_create_dumb *args);
609 int radeon_mode_dumb_mmap(struct drm_file *filp,
610 struct drm_device *dev,
611 uint32_t handle, uint64_t *offset_p);
612
613 /*
614 * Semaphores.
615 */
616 struct radeon_semaphore {
617 struct radeon_sa_bo *sa_bo;
618 signed waiters;
619 uint64_t gpu_addr;
620 };
621
622 int radeon_semaphore_create(struct radeon_device *rdev,
623 struct radeon_semaphore **semaphore);
624 bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
625 struct radeon_semaphore *semaphore);
626 bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
627 struct radeon_semaphore *semaphore);
628 void radeon_semaphore_free(struct radeon_device *rdev,
629 struct radeon_semaphore **semaphore,
630 struct radeon_fence *fence);
631
632 /*
633 * Synchronization
634 */
635 struct radeon_sync {
636 struct radeon_semaphore *semaphores[RADEON_NUM_SYNCS];
637 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
638 struct radeon_fence *last_vm_update;
639 };
640
641 void radeon_sync_create(struct radeon_sync *sync);
642 void radeon_sync_fence(struct radeon_sync *sync,
643 struct radeon_fence *fence);
644 int radeon_sync_resv(struct radeon_device *rdev,
645 struct radeon_sync *sync,
646 struct dma_resv *resv,
647 bool shared);
648 int radeon_sync_rings(struct radeon_device *rdev,
649 struct radeon_sync *sync,
650 int waiting_ring);
651 void radeon_sync_free(struct radeon_device *rdev, struct radeon_sync *sync,
652 struct radeon_fence *fence);
653
654 /*
655 * GART structures, functions & helpers
656 */
657 struct radeon_mc;
658
659 #define RADEON_GPU_PAGE_SIZE 4096
660 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
661 #define RADEON_GPU_PAGE_SHIFT 12
662 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
663
664 #define RADEON_GART_PAGE_DUMMY 0
665 #define RADEON_GART_PAGE_VALID (1 << 0)
666 #define RADEON_GART_PAGE_READ (1 << 1)
667 #define RADEON_GART_PAGE_WRITE (1 << 2)
668 #define RADEON_GART_PAGE_SNOOP (1 << 3)
669
670 struct radeon_gart {
671 #ifdef __NetBSD__
672 bus_dma_segment_t rg_table_seg;
673 bus_dmamap_t rg_table_map;
674 #endif
675 dma_addr_t table_addr;
676 struct radeon_bo *robj;
677 void *ptr;
678 unsigned num_gpu_pages;
679 unsigned num_cpu_pages;
680 unsigned table_size;
681 struct page **pages;
682 uint64_t *pages_entry;
683 bool ready;
684 };
685
686 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
687 void radeon_gart_table_ram_free(struct radeon_device *rdev);
688 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
689 void radeon_gart_table_vram_free(struct radeon_device *rdev);
690 int radeon_gart_table_vram_pin(struct radeon_device *rdev);
691 void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
692 int radeon_gart_init(struct radeon_device *rdev);
693 void radeon_gart_fini(struct radeon_device *rdev);
694 #ifdef __NetBSD__
695 void radeon_gart_unbind(struct radeon_device *rdev, unsigned gpu_start,
696 unsigned npages);
697 int radeon_gart_bind(struct radeon_device *rdev, unsigned gpu_start,
698 unsigned npages, struct page **pages,
699 bus_dmamap_t dmamap, uint32_t flags);
700 #else
701 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
702 int pages);
703 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
704 int pages, struct page **pagelist,
705 dma_addr_t *dma_addr, uint32_t flags);
706 #endif
707
708
709 /*
710 * GPU MC structures, functions & helpers
711 */
712 struct radeon_mc {
713 resource_size_t aper_size;
714 resource_size_t aper_base;
715 resource_size_t agp_base;
716 /* for some chips with <= 32MB we need to lie
717 * about vram size near mc fb location */
718 u64 mc_vram_size;
719 u64 visible_vram_size;
720 u64 gtt_size;
721 u64 gtt_start;
722 u64 gtt_end;
723 u64 vram_start;
724 u64 vram_end;
725 unsigned vram_width;
726 u64 real_vram_size;
727 int vram_mtrr;
728 bool vram_is_ddr;
729 bool igp_sideport_enabled;
730 u64 gtt_base_align;
731 u64 mc_mask;
732 };
733
734 bool radeon_combios_sideport_present(struct radeon_device *rdev);
735 bool radeon_atombios_sideport_present(struct radeon_device *rdev);
736
737 /*
738 * GPU scratch registers structures, functions & helpers
739 */
740 struct radeon_scratch {
741 unsigned num_reg;
742 uint32_t reg_base;
743 bool free[32];
744 uint32_t reg[32];
745 };
746
747 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
748 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
749
750 /*
751 * GPU doorbell structures, functions & helpers
752 */
753 #define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */
754
755 struct radeon_doorbell {
756 /* doorbell mmio */
757 resource_size_t base;
758 resource_size_t size;
759 #ifdef __NetBSD__
760 bus_space_tag_t bst;
761 bus_space_handle_t bsh;
762 #else
763 u32 __iomem *ptr;
764 #endif
765 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */
766 DECLARE_BITMAP(used, RADEON_MAX_DOORBELLS);
767 };
768
769 int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
770 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
771
772 /*
773 * IRQS.
774 */
775
776 struct radeon_flip_work {
777 struct work_struct flip_work;
778 struct work_struct unpin_work;
779 struct radeon_device *rdev;
780 int crtc_id;
781 u32 target_vblank;
782 uint64_t base;
783 struct drm_pending_vblank_event *event;
784 struct radeon_bo *old_rbo;
785 struct dma_fence *fence;
786 bool async;
787 };
788
789 struct r500_irq_stat_regs {
790 u32 disp_int;
791 u32 hdmi0_status;
792 };
793
794 struct r600_irq_stat_regs {
795 u32 disp_int;
796 u32 disp_int_cont;
797 u32 disp_int_cont2;
798 u32 d1grph_int;
799 u32 d2grph_int;
800 u32 hdmi0_status;
801 u32 hdmi1_status;
802 };
803
804 struct evergreen_irq_stat_regs {
805 u32 disp_int[6];
806 u32 grph_int[6];
807 u32 afmt_status[6];
808 };
809
810 struct cik_irq_stat_regs {
811 u32 disp_int;
812 u32 disp_int_cont;
813 u32 disp_int_cont2;
814 u32 disp_int_cont3;
815 u32 disp_int_cont4;
816 u32 disp_int_cont5;
817 u32 disp_int_cont6;
818 u32 d1grph_int;
819 u32 d2grph_int;
820 u32 d3grph_int;
821 u32 d4grph_int;
822 u32 d5grph_int;
823 u32 d6grph_int;
824 };
825
826 union radeon_irq_stat_regs {
827 struct r500_irq_stat_regs r500;
828 struct r600_irq_stat_regs r600;
829 struct evergreen_irq_stat_regs evergreen;
830 struct cik_irq_stat_regs cik;
831 };
832
833 struct radeon_irq {
834 bool installed;
835 spinlock_t lock;
836 atomic_t ring_int[RADEON_NUM_RINGS];
837 bool crtc_vblank_int[RADEON_MAX_CRTCS];
838 atomic_t pflip[RADEON_MAX_CRTCS];
839 #ifdef __NetBSD__
840 spinlock_t vblank_lock;
841 drm_waitqueue_t vblank_queue;
842 #else
843 wait_queue_head_t vblank_queue;
844 #endif
845 bool hpd[RADEON_MAX_HPD_PINS];
846 bool afmt[RADEON_MAX_AFMT_BLOCKS];
847 union radeon_irq_stat_regs stat_regs;
848 bool dpm_thermal;
849 };
850
851 int radeon_irq_kms_init(struct radeon_device *rdev);
852 void radeon_irq_kms_fini(struct radeon_device *rdev);
853 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
854 bool radeon_irq_kms_sw_irq_get_delayed(struct radeon_device *rdev, int ring);
855 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
856 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
857 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
858 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
859 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
860 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
861 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
862
863 /*
864 * CP & rings.
865 */
866
867 struct radeon_ib {
868 struct radeon_sa_bo *sa_bo;
869 uint32_t length_dw;
870 uint64_t gpu_addr;
871 uint32_t *ptr;
872 int ring;
873 struct radeon_fence *fence;
874 struct radeon_vm *vm;
875 bool is_const_ib;
876 struct radeon_sync sync;
877 };
878
879 struct radeon_ring {
880 struct radeon_bo *ring_obj;
881 volatile uint32_t *ring;
882 unsigned rptr_offs;
883 unsigned rptr_save_reg;
884 u64 next_rptr_gpu_addr;
885 volatile u32 *next_rptr_cpu_addr;
886 unsigned wptr;
887 unsigned wptr_old;
888 unsigned ring_size;
889 unsigned ring_free_dw;
890 int count_dw;
891 atomic_t last_rptr;
892 atomic64_t last_activity;
893 uint64_t gpu_addr;
894 uint32_t align_mask;
895 uint32_t ptr_mask;
896 bool ready;
897 u32 nop;
898 u32 idx;
899 u64 last_semaphore_signal_addr;
900 u64 last_semaphore_wait_addr;
901 /* for CIK queues */
902 u32 me;
903 u32 pipe;
904 u32 queue;
905 struct radeon_bo *mqd_obj;
906 u32 doorbell_index;
907 unsigned wptr_offs;
908 };
909
910 struct radeon_mec {
911 struct radeon_bo *hpd_eop_obj;
912 u64 hpd_eop_gpu_addr;
913 u32 num_pipe;
914 u32 num_mec;
915 u32 num_queue;
916 };
917
918 /*
919 * VM
920 */
921
922 /* maximum number of VMIDs */
923 #define RADEON_NUM_VM 16
924
925 /* number of entries in page table */
926 #define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size)
927
928 /* PTBs (Page Table Blocks) need to be aligned to 32K */
929 #define RADEON_VM_PTB_ALIGN_SIZE 32768
930 #define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1)
931 #define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK)
932
933 #define R600_PTE_VALID (1 << 0)
934 #define R600_PTE_SYSTEM (1 << 1)
935 #define R600_PTE_SNOOPED (1 << 2)
936 #define R600_PTE_READABLE (1 << 5)
937 #define R600_PTE_WRITEABLE (1 << 6)
938
939 /* PTE (Page Table Entry) fragment field for different page sizes */
940 #define R600_PTE_FRAG_4KB (0 << 7)
941 #define R600_PTE_FRAG_64KB (4 << 7)
942 #define R600_PTE_FRAG_256KB (6 << 7)
943
944 /* flags needed to be set so we can copy directly from the GART table */
945 #define R600_PTE_GART_MASK ( R600_PTE_READABLE | R600_PTE_WRITEABLE | \
946 R600_PTE_SYSTEM | R600_PTE_VALID )
947
948 struct radeon_vm_pt {
949 struct radeon_bo *bo;
950 uint64_t addr;
951 };
952
953 struct radeon_vm_id {
954 unsigned id;
955 uint64_t pd_gpu_addr;
956 /* last flushed PD/PT update */
957 struct radeon_fence *flushed_updates;
958 /* last use of vmid */
959 struct radeon_fence *last_id_use;
960 };
961
962 struct radeon_vm {
963 struct mutex mutex;
964
965 struct rb_root_cached va;
966
967 /* protecting invalidated and freed */
968 spinlock_t status_lock;
969
970 /* BOs moved, but not yet updated in the PT */
971 struct list_head invalidated;
972
973 /* BOs freed, but not yet updated in the PT */
974 struct list_head freed;
975
976 /* BOs cleared in the PT */
977 struct list_head cleared;
978
979 /* contains the page directory */
980 struct radeon_bo *page_directory;
981 unsigned max_pde_used;
982
983 /* array of page tables, one for each page directory entry */
984 struct radeon_vm_pt *page_tables;
985
986 struct radeon_bo_va *ib_bo_va;
987
988 /* for id and flush management per ring */
989 struct radeon_vm_id ids[RADEON_NUM_RINGS];
990 };
991
992 struct radeon_vm_manager {
993 struct radeon_fence *active[RADEON_NUM_VM];
994 uint32_t max_pfn;
995 /* number of VMIDs */
996 unsigned nvm;
997 /* vram base address for page table entry */
998 u64 vram_base_offset;
999 /* is vm enabled? */
1000 bool enabled;
1001 /* for hw to save the PD addr on suspend/resume */
1002 uint32_t saved_table_addr[RADEON_NUM_VM];
1003 };
1004
1005 /*
1006 * file private structure
1007 */
1008 struct radeon_fpriv {
1009 struct radeon_vm vm;
1010 };
1011
1012 /*
1013 * R6xx+ IH ring
1014 */
1015 struct r600_ih {
1016 struct radeon_bo *ring_obj;
1017 volatile uint32_t *ring;
1018 unsigned rptr;
1019 unsigned ring_size;
1020 uint64_t gpu_addr;
1021 uint32_t ptr_mask;
1022 atomic_t lock;
1023 bool enabled;
1024 };
1025
1026 /*
1027 * RLC stuff
1028 */
1029 #include "clearstate_defs.h"
1030
1031 struct radeon_rlc {
1032 /* for power gating */
1033 struct radeon_bo *save_restore_obj;
1034 uint64_t save_restore_gpu_addr;
1035 volatile uint32_t *sr_ptr;
1036 const u32 *reg_list;
1037 u32 reg_list_size;
1038 /* for clear state */
1039 struct radeon_bo *clear_state_obj;
1040 uint64_t clear_state_gpu_addr;
1041 volatile uint32_t *cs_ptr;
1042 const struct cs_section_def *cs_data;
1043 u32 clear_state_size;
1044 /* for cp tables */
1045 struct radeon_bo *cp_table_obj;
1046 uint64_t cp_table_gpu_addr;
1047 volatile uint32_t *cp_table_ptr;
1048 u32 cp_table_size;
1049 };
1050
1051 int radeon_ib_get(struct radeon_device *rdev, int ring,
1052 struct radeon_ib *ib, struct radeon_vm *vm,
1053 unsigned size);
1054 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
1055 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
1056 struct radeon_ib *const_ib, bool hdp_flush);
1057 int radeon_ib_pool_init(struct radeon_device *rdev);
1058 void radeon_ib_pool_fini(struct radeon_device *rdev);
1059 int radeon_ib_ring_tests(struct radeon_device *rdev);
1060 /* Ring access between begin & end cannot sleep */
1061 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
1062 struct radeon_ring *ring);
1063 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
1064 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
1065 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
1066 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp,
1067 bool hdp_flush);
1068 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp,
1069 bool hdp_flush);
1070 void radeon_ring_undo(struct radeon_ring *ring);
1071 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
1072 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
1073 void radeon_ring_lockup_update(struct radeon_device *rdev,
1074 struct radeon_ring *ring);
1075 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
1076 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
1077 uint32_t **data);
1078 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
1079 unsigned size, uint32_t *data);
1080 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
1081 unsigned rptr_offs, u32 nop);
1082 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
1083
1084
1085 /* r600 async dma */
1086 void r600_dma_stop(struct radeon_device *rdev);
1087 int r600_dma_resume(struct radeon_device *rdev);
1088 void r600_dma_fini(struct radeon_device *rdev);
1089
1090 void cayman_dma_stop(struct radeon_device *rdev);
1091 int cayman_dma_resume(struct radeon_device *rdev);
1092 void cayman_dma_fini(struct radeon_device *rdev);
1093
1094 /*
1095 * CS.
1096 */
1097 struct radeon_cs_chunk {
1098 uint32_t length_dw;
1099 uint32_t *kdata;
1100 void __user *user_ptr;
1101 };
1102
1103 struct radeon_cs_parser {
1104 struct device *dev;
1105 struct radeon_device *rdev;
1106 struct drm_file *filp;
1107 /* chunks */
1108 unsigned nchunks;
1109 struct radeon_cs_chunk *chunks;
1110 uint64_t *chunks_array;
1111 /* IB */
1112 unsigned idx;
1113 /* relocations */
1114 unsigned nrelocs;
1115 struct radeon_bo_list *relocs;
1116 struct radeon_bo_list *vm_bos;
1117 struct list_head validated;
1118 unsigned dma_reloc_idx;
1119 /* indices of various chunks */
1120 struct radeon_cs_chunk *chunk_ib;
1121 struct radeon_cs_chunk *chunk_relocs;
1122 struct radeon_cs_chunk *chunk_flags;
1123 struct radeon_cs_chunk *chunk_const_ib;
1124 struct radeon_ib ib;
1125 struct radeon_ib const_ib;
1126 void *track;
1127 unsigned family;
1128 int parser_error;
1129 u32 cs_flags;
1130 u32 ring;
1131 s32 priority;
1132 struct ww_acquire_ctx ticket;
1133 };
1134
radeon_get_ib_value(struct radeon_cs_parser * p,int idx)1135 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
1136 {
1137 struct radeon_cs_chunk *ibc = p->chunk_ib;
1138
1139 if (ibc->kdata)
1140 return ibc->kdata[idx];
1141 return p->ib.ptr[idx];
1142 }
1143
1144
1145 struct radeon_cs_packet {
1146 unsigned idx;
1147 unsigned type;
1148 unsigned reg;
1149 unsigned opcode;
1150 int count;
1151 unsigned one_reg_wr;
1152 };
1153
1154 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
1155 struct radeon_cs_packet *pkt,
1156 unsigned idx, unsigned reg);
1157 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
1158 struct radeon_cs_packet *pkt);
1159
1160
1161 /*
1162 * AGP
1163 */
1164 int radeon_agp_init(struct radeon_device *rdev);
1165 void radeon_agp_resume(struct radeon_device *rdev);
1166 void radeon_agp_suspend(struct radeon_device *rdev);
1167 void radeon_agp_fini(struct radeon_device *rdev);
1168
1169
1170 /*
1171 * Writeback
1172 */
1173 struct radeon_wb {
1174 struct radeon_bo *wb_obj;
1175 volatile uint32_t *wb;
1176 uint64_t gpu_addr;
1177 bool enabled;
1178 bool use_event;
1179 };
1180
1181 #define RADEON_WB_SCRATCH_OFFSET 0
1182 #define RADEON_WB_RING0_NEXT_RPTR 256
1183 #define RADEON_WB_CP_RPTR_OFFSET 1024
1184 #define RADEON_WB_CP1_RPTR_OFFSET 1280
1185 #define RADEON_WB_CP2_RPTR_OFFSET 1536
1186 #define R600_WB_DMA_RPTR_OFFSET 1792
1187 #define R600_WB_IH_WPTR_OFFSET 2048
1188 #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
1189 #define R600_WB_EVENT_OFFSET 3072
1190 #define CIK_WB_CP1_WPTR_OFFSET 3328
1191 #define CIK_WB_CP2_WPTR_OFFSET 3584
1192 #define R600_WB_DMA_RING_TEST_OFFSET 3588
1193 #define CAYMAN_WB_DMA1_RING_TEST_OFFSET 3592
1194
1195 /**
1196 * struct radeon_pm - power management datas
1197 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
1198 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
1199 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
1200 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
1201 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
1202 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
1203 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
1204 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
1205 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
1206 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
1207 * @needed_bandwidth: current bandwidth needs
1208 *
1209 * It keeps track of various data needed to take powermanagement decision.
1210 * Bandwidth need is used to determine minimun clock of the GPU and memory.
1211 * Equation between gpu/memory clock and available bandwidth is hw dependent
1212 * (type of memory, bus size, efficiency, ...)
1213 */
1214
1215 enum radeon_pm_method {
1216 PM_METHOD_PROFILE,
1217 PM_METHOD_DYNPM,
1218 PM_METHOD_DPM,
1219 };
1220
1221 enum radeon_dynpm_state {
1222 DYNPM_STATE_DISABLED,
1223 DYNPM_STATE_MINIMUM,
1224 DYNPM_STATE_PAUSED,
1225 DYNPM_STATE_ACTIVE,
1226 DYNPM_STATE_SUSPENDED,
1227 };
1228 enum radeon_dynpm_action {
1229 DYNPM_ACTION_NONE,
1230 DYNPM_ACTION_MINIMUM,
1231 DYNPM_ACTION_DOWNCLOCK,
1232 DYNPM_ACTION_UPCLOCK,
1233 DYNPM_ACTION_DEFAULT
1234 };
1235
1236 enum radeon_voltage_type {
1237 VOLTAGE_NONE = 0,
1238 VOLTAGE_GPIO,
1239 VOLTAGE_VDDC,
1240 VOLTAGE_SW
1241 };
1242
1243 enum radeon_pm_state_type {
1244 /* not used for dpm */
1245 POWER_STATE_TYPE_DEFAULT,
1246 POWER_STATE_TYPE_POWERSAVE,
1247 /* user selectable states */
1248 POWER_STATE_TYPE_BATTERY,
1249 POWER_STATE_TYPE_BALANCED,
1250 POWER_STATE_TYPE_PERFORMANCE,
1251 /* internal states */
1252 POWER_STATE_TYPE_INTERNAL_UVD,
1253 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1254 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1255 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1256 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1257 POWER_STATE_TYPE_INTERNAL_BOOT,
1258 POWER_STATE_TYPE_INTERNAL_THERMAL,
1259 POWER_STATE_TYPE_INTERNAL_ACPI,
1260 POWER_STATE_TYPE_INTERNAL_ULV,
1261 POWER_STATE_TYPE_INTERNAL_3DPERF,
1262 };
1263
1264 enum radeon_pm_profile_type {
1265 PM_PROFILE_DEFAULT,
1266 PM_PROFILE_AUTO,
1267 PM_PROFILE_LOW,
1268 PM_PROFILE_MID,
1269 PM_PROFILE_HIGH,
1270 };
1271
1272 #define PM_PROFILE_DEFAULT_IDX 0
1273 #define PM_PROFILE_LOW_SH_IDX 1
1274 #define PM_PROFILE_MID_SH_IDX 2
1275 #define PM_PROFILE_HIGH_SH_IDX 3
1276 #define PM_PROFILE_LOW_MH_IDX 4
1277 #define PM_PROFILE_MID_MH_IDX 5
1278 #define PM_PROFILE_HIGH_MH_IDX 6
1279 #define PM_PROFILE_MAX 7
1280
1281 struct radeon_pm_profile {
1282 int dpms_off_ps_idx;
1283 int dpms_on_ps_idx;
1284 int dpms_off_cm_idx;
1285 int dpms_on_cm_idx;
1286 };
1287
1288 enum radeon_int_thermal_type {
1289 THERMAL_TYPE_NONE,
1290 THERMAL_TYPE_EXTERNAL,
1291 THERMAL_TYPE_EXTERNAL_GPIO,
1292 THERMAL_TYPE_RV6XX,
1293 THERMAL_TYPE_RV770,
1294 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1295 THERMAL_TYPE_EVERGREEN,
1296 THERMAL_TYPE_SUMO,
1297 THERMAL_TYPE_NI,
1298 THERMAL_TYPE_SI,
1299 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
1300 THERMAL_TYPE_CI,
1301 THERMAL_TYPE_KV,
1302 };
1303
1304 struct radeon_voltage {
1305 enum radeon_voltage_type type;
1306 /* gpio voltage */
1307 struct radeon_gpio_rec gpio;
1308 u32 delay; /* delay in usec from voltage drop to sclk change */
1309 bool active_high; /* voltage drop is active when bit is high */
1310 /* VDDC voltage */
1311 u8 vddc_id; /* index into vddc voltage table */
1312 u8 vddci_id; /* index into vddci voltage table */
1313 bool vddci_enabled;
1314 /* r6xx+ sw */
1315 u16 voltage;
1316 /* evergreen+ vddci */
1317 u16 vddci;
1318 };
1319
1320 /* clock mode flags */
1321 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1322
1323 struct radeon_pm_clock_info {
1324 /* memory clock */
1325 u32 mclk;
1326 /* engine clock */
1327 u32 sclk;
1328 /* voltage info */
1329 struct radeon_voltage voltage;
1330 /* standardized clock flags */
1331 u32 flags;
1332 };
1333
1334 /* state flags */
1335 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
1336
1337 struct radeon_power_state {
1338 enum radeon_pm_state_type type;
1339 struct radeon_pm_clock_info *clock_info;
1340 /* number of valid clock modes in this power state */
1341 int num_clock_modes;
1342 struct radeon_pm_clock_info *default_clock_mode;
1343 /* standardized state flags */
1344 u32 flags;
1345 u32 misc; /* vbios specific flags */
1346 u32 misc2; /* vbios specific flags */
1347 int pcie_lanes; /* pcie lanes */
1348 };
1349
1350 /*
1351 * Some modes are overclocked by very low value, accept them
1352 */
1353 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1354
1355 enum radeon_dpm_auto_throttle_src {
1356 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL,
1357 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1358 };
1359
1360 enum radeon_dpm_event_src {
1361 RADEON_DPM_EVENT_SRC_ANALOG = 0,
1362 RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
1363 RADEON_DPM_EVENT_SRC_DIGITAL = 2,
1364 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1365 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1366 };
1367
1368 #define RADEON_MAX_VCE_LEVELS 6
1369
1370 enum radeon_vce_level {
1371 RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1372 RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1373 RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1374 RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1375 RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1376 RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1377 };
1378
1379 struct radeon_ps {
1380 u32 caps; /* vbios flags */
1381 u32 class; /* vbios flags */
1382 u32 class2; /* vbios flags */
1383 /* UVD clocks */
1384 u32 vclk;
1385 u32 dclk;
1386 /* VCE clocks */
1387 u32 evclk;
1388 u32 ecclk;
1389 bool vce_active;
1390 enum radeon_vce_level vce_level;
1391 /* asic priv */
1392 void *ps_priv;
1393 };
1394
1395 struct radeon_dpm_thermal {
1396 /* thermal interrupt work */
1397 struct work_struct work;
1398 /* low temperature threshold */
1399 int min_temp;
1400 /* high temperature threshold */
1401 int max_temp;
1402 /* was interrupt low to high or high to low */
1403 bool high_to_low;
1404 };
1405
1406 enum radeon_clk_action
1407 {
1408 RADEON_SCLK_UP = 1,
1409 RADEON_SCLK_DOWN
1410 };
1411
1412 struct radeon_blacklist_clocks
1413 {
1414 u32 sclk;
1415 u32 mclk;
1416 enum radeon_clk_action action;
1417 };
1418
1419 struct radeon_clock_and_voltage_limits {
1420 u32 sclk;
1421 u32 mclk;
1422 u16 vddc;
1423 u16 vddci;
1424 };
1425
1426 struct radeon_clock_array {
1427 u32 count;
1428 u32 *values;
1429 };
1430
1431 struct radeon_clock_voltage_dependency_entry {
1432 u32 clk;
1433 u16 v;
1434 };
1435
1436 struct radeon_clock_voltage_dependency_table {
1437 u32 count;
1438 struct radeon_clock_voltage_dependency_entry *entries;
1439 };
1440
1441 union radeon_cac_leakage_entry {
1442 struct {
1443 u16 vddc;
1444 u32 leakage;
1445 };
1446 struct {
1447 u16 vddc1;
1448 u16 vddc2;
1449 u16 vddc3;
1450 };
1451 };
1452
1453 struct radeon_cac_leakage_table {
1454 u32 count;
1455 union radeon_cac_leakage_entry *entries;
1456 };
1457
1458 struct radeon_phase_shedding_limits_entry {
1459 u16 voltage;
1460 u32 sclk;
1461 u32 mclk;
1462 };
1463
1464 struct radeon_phase_shedding_limits_table {
1465 u32 count;
1466 struct radeon_phase_shedding_limits_entry *entries;
1467 };
1468
1469 struct radeon_uvd_clock_voltage_dependency_entry {
1470 u32 vclk;
1471 u32 dclk;
1472 u16 v;
1473 };
1474
1475 struct radeon_uvd_clock_voltage_dependency_table {
1476 u8 count;
1477 struct radeon_uvd_clock_voltage_dependency_entry *entries;
1478 };
1479
1480 struct radeon_vce_clock_voltage_dependency_entry {
1481 u32 ecclk;
1482 u32 evclk;
1483 u16 v;
1484 };
1485
1486 struct radeon_vce_clock_voltage_dependency_table {
1487 u8 count;
1488 struct radeon_vce_clock_voltage_dependency_entry *entries;
1489 };
1490
1491 struct radeon_ppm_table {
1492 u8 ppm_design;
1493 u16 cpu_core_number;
1494 u32 platform_tdp;
1495 u32 small_ac_platform_tdp;
1496 u32 platform_tdc;
1497 u32 small_ac_platform_tdc;
1498 u32 apu_tdp;
1499 u32 dgpu_tdp;
1500 u32 dgpu_ulv_power;
1501 u32 tj_max;
1502 };
1503
1504 struct radeon_cac_tdp_table {
1505 u16 tdp;
1506 u16 configurable_tdp;
1507 u16 tdc;
1508 u16 battery_power_limit;
1509 u16 small_power_limit;
1510 u16 low_cac_leakage;
1511 u16 high_cac_leakage;
1512 u16 maximum_power_delivery_limit;
1513 };
1514
1515 struct radeon_dpm_dynamic_state {
1516 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
1517 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
1518 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
1519 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk;
1520 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk;
1521 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
1522 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
1523 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1524 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
1525 struct radeon_clock_array valid_sclk_values;
1526 struct radeon_clock_array valid_mclk_values;
1527 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
1528 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac;
1529 u32 mclk_sclk_ratio;
1530 u32 sclk_mclk_delta;
1531 u16 vddc_vddci_delta;
1532 u16 min_vddc_for_pcie_gen2;
1533 struct radeon_cac_leakage_table cac_leakage_table;
1534 struct radeon_phase_shedding_limits_table phase_shedding_limits_table;
1535 struct radeon_ppm_table *ppm_table;
1536 struct radeon_cac_tdp_table *cac_tdp_table;
1537 };
1538
1539 struct radeon_dpm_fan {
1540 u16 t_min;
1541 u16 t_med;
1542 u16 t_high;
1543 u16 pwm_min;
1544 u16 pwm_med;
1545 u16 pwm_high;
1546 u8 t_hyst;
1547 u32 cycle_delay;
1548 u16 t_max;
1549 u8 control_mode;
1550 u16 default_max_fan_pwm;
1551 u16 default_fan_output_sensitivity;
1552 u16 fan_output_sensitivity;
1553 bool ucode_fan_control;
1554 };
1555
1556 enum radeon_pcie_gen {
1557 RADEON_PCIE_GEN1 = 0,
1558 RADEON_PCIE_GEN2 = 1,
1559 RADEON_PCIE_GEN3 = 2,
1560 RADEON_PCIE_GEN_INVALID = 0xffff
1561 };
1562
1563 enum radeon_dpm_forced_level {
1564 RADEON_DPM_FORCED_LEVEL_AUTO = 0,
1565 RADEON_DPM_FORCED_LEVEL_LOW = 1,
1566 RADEON_DPM_FORCED_LEVEL_HIGH = 2,
1567 };
1568
1569 struct radeon_vce_state {
1570 /* vce clocks */
1571 u32 evclk;
1572 u32 ecclk;
1573 /* gpu clocks */
1574 u32 sclk;
1575 u32 mclk;
1576 u8 clk_idx;
1577 u8 pstate;
1578 };
1579
1580 struct radeon_dpm {
1581 struct radeon_ps *ps;
1582 /* number of valid power states */
1583 int num_ps;
1584 /* current power state that is active */
1585 struct radeon_ps *current_ps;
1586 /* requested power state */
1587 struct radeon_ps *requested_ps;
1588 /* boot up power state */
1589 struct radeon_ps *boot_ps;
1590 /* default uvd power state */
1591 struct radeon_ps *uvd_ps;
1592 /* vce requirements */
1593 struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS];
1594 enum radeon_vce_level vce_level;
1595 enum radeon_pm_state_type state;
1596 enum radeon_pm_state_type user_state;
1597 u32 platform_caps;
1598 u32 voltage_response_time;
1599 u32 backbias_response_time;
1600 void *priv;
1601 u32 new_active_crtcs;
1602 int new_active_crtc_count;
1603 u32 current_active_crtcs;
1604 int current_active_crtc_count;
1605 bool single_display;
1606 struct radeon_dpm_dynamic_state dyn_state;
1607 struct radeon_dpm_fan fan;
1608 u32 tdp_limit;
1609 u32 near_tdp_limit;
1610 u32 near_tdp_limit_adjusted;
1611 u32 sq_ramping_threshold;
1612 u32 cac_leakage;
1613 u16 tdp_od_limit;
1614 u32 tdp_adjustment;
1615 u16 load_line_slope;
1616 bool power_control;
1617 bool ac_power;
1618 /* special states active */
1619 bool thermal_active;
1620 bool uvd_active;
1621 bool vce_active;
1622 /* thermal handling */
1623 struct radeon_dpm_thermal thermal;
1624 /* forced levels */
1625 enum radeon_dpm_forced_level forced_level;
1626 /* track UVD streams */
1627 unsigned sd;
1628 unsigned hd;
1629 };
1630
1631 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable);
1632 void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable);
1633
1634 struct radeon_pm {
1635 struct mutex mutex;
1636 /* write locked while reprogramming mclk */
1637 struct rw_semaphore mclk_lock;
1638 u32 active_crtcs;
1639 int active_crtc_count;
1640 int req_vblank;
1641 bool vblank_sync;
1642 fixed20_12 max_bandwidth;
1643 fixed20_12 igp_sideport_mclk;
1644 fixed20_12 igp_system_mclk;
1645 fixed20_12 igp_ht_link_clk;
1646 fixed20_12 igp_ht_link_width;
1647 fixed20_12 k8_bandwidth;
1648 fixed20_12 sideport_bandwidth;
1649 fixed20_12 ht_bandwidth;
1650 fixed20_12 core_bandwidth;
1651 fixed20_12 sclk;
1652 fixed20_12 mclk;
1653 fixed20_12 needed_bandwidth;
1654 struct radeon_power_state *power_state;
1655 /* number of valid power states */
1656 int num_power_states;
1657 int current_power_state_index;
1658 int current_clock_mode_index;
1659 int requested_power_state_index;
1660 int requested_clock_mode_index;
1661 int default_power_state_index;
1662 u32 current_sclk;
1663 u32 current_mclk;
1664 u16 current_vddc;
1665 u16 current_vddci;
1666 u32 default_sclk;
1667 u32 default_mclk;
1668 u16 default_vddc;
1669 u16 default_vddci;
1670 struct radeon_i2c_chan *i2c_bus;
1671 /* selected pm method */
1672 enum radeon_pm_method pm_method;
1673 /* dynpm power management */
1674 struct delayed_work dynpm_idle_work;
1675 enum radeon_dynpm_state dynpm_state;
1676 enum radeon_dynpm_action dynpm_planned_action;
1677 unsigned long dynpm_action_timeout;
1678 bool dynpm_can_upclock;
1679 bool dynpm_can_downclock;
1680 /* profile-based power management */
1681 enum radeon_pm_profile_type profile;
1682 int profile_index;
1683 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
1684 /* internal thermal controller on rv6xx+ */
1685 enum radeon_int_thermal_type int_thermal_type;
1686 struct device *int_hwmon_dev;
1687 /* fan control parameters */
1688 bool no_fan;
1689 u8 fan_pulses_per_revolution;
1690 u8 fan_min_rpm;
1691 u8 fan_max_rpm;
1692 /* dpm */
1693 bool dpm_enabled;
1694 bool sysfs_initialized;
1695 struct radeon_dpm dpm;
1696 };
1697
1698 #define RADEON_PCIE_SPEED_25 1
1699 #define RADEON_PCIE_SPEED_50 2
1700 #define RADEON_PCIE_SPEED_80 4
1701
1702 int radeon_pm_get_type_index(struct radeon_device *rdev,
1703 enum radeon_pm_state_type ps_type,
1704 int instance);
1705 /*
1706 * UVD
1707 */
1708 #define RADEON_DEFAULT_UVD_HANDLES 10
1709 #define RADEON_MAX_UVD_HANDLES 30
1710 #define RADEON_UVD_STACK_SIZE (200*1024)
1711 #define RADEON_UVD_HEAP_SIZE (256*1024)
1712 #define RADEON_UVD_SESSION_SIZE (50*1024)
1713
1714 struct radeon_uvd {
1715 bool fw_header_present;
1716 struct radeon_bo *vcpu_bo;
1717 void *cpu_addr;
1718 uint64_t gpu_addr;
1719 unsigned max_handles;
1720 atomic_t handles[RADEON_MAX_UVD_HANDLES];
1721 struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
1722 unsigned img_size[RADEON_MAX_UVD_HANDLES];
1723 struct delayed_work idle_work;
1724 };
1725
1726 int radeon_uvd_init(struct radeon_device *rdev);
1727 void radeon_uvd_fini(struct radeon_device *rdev);
1728 int radeon_uvd_suspend(struct radeon_device *rdev);
1729 int radeon_uvd_resume(struct radeon_device *rdev);
1730 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1731 uint32_t handle, struct radeon_fence **fence);
1732 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1733 uint32_t handle, struct radeon_fence **fence);
1734 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo,
1735 uint32_t allowed_domains);
1736 void radeon_uvd_free_handles(struct radeon_device *rdev,
1737 struct drm_file *filp);
1738 int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
1739 void radeon_uvd_note_usage(struct radeon_device *rdev);
1740 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1741 unsigned vclk, unsigned dclk,
1742 unsigned vco_min, unsigned vco_max,
1743 unsigned fb_factor, unsigned fb_mask,
1744 unsigned pd_min, unsigned pd_max,
1745 unsigned pd_even,
1746 unsigned *optimal_fb_div,
1747 unsigned *optimal_vclk_div,
1748 unsigned *optimal_dclk_div);
1749 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1750 unsigned cg_upll_func_cntl);
1751
1752 /*
1753 * VCE
1754 */
1755 #define RADEON_MAX_VCE_HANDLES 16
1756
1757 struct radeon_vce {
1758 struct radeon_bo *vcpu_bo;
1759 uint64_t gpu_addr;
1760 unsigned fw_version;
1761 unsigned fb_version;
1762 atomic_t handles[RADEON_MAX_VCE_HANDLES];
1763 struct drm_file *filp[RADEON_MAX_VCE_HANDLES];
1764 unsigned img_size[RADEON_MAX_VCE_HANDLES];
1765 struct delayed_work idle_work;
1766 uint32_t keyselect;
1767 };
1768
1769 int radeon_vce_init(struct radeon_device *rdev);
1770 void radeon_vce_fini(struct radeon_device *rdev);
1771 int radeon_vce_suspend(struct radeon_device *rdev);
1772 int radeon_vce_resume(struct radeon_device *rdev);
1773 int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring,
1774 uint32_t handle, struct radeon_fence **fence);
1775 int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring,
1776 uint32_t handle, struct radeon_fence **fence);
1777 void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp);
1778 void radeon_vce_note_usage(struct radeon_device *rdev);
1779 int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size);
1780 int radeon_vce_cs_parse(struct radeon_cs_parser *p);
1781 bool radeon_vce_semaphore_emit(struct radeon_device *rdev,
1782 struct radeon_ring *ring,
1783 struct radeon_semaphore *semaphore,
1784 bool emit_wait);
1785 void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
1786 void radeon_vce_fence_emit(struct radeon_device *rdev,
1787 struct radeon_fence *fence);
1788 int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
1789 int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
1790
1791 struct r600_audio_pin {
1792 int channels;
1793 int rate;
1794 int bits_per_sample;
1795 u8 status_bits;
1796 u8 category_code;
1797 u32 offset;
1798 bool connected;
1799 u32 id;
1800 };
1801
1802 struct r600_audio {
1803 bool enabled;
1804 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS];
1805 int num_pins;
1806 struct radeon_audio_funcs *hdmi_funcs;
1807 struct radeon_audio_funcs *dp_funcs;
1808 struct radeon_audio_basic_funcs *funcs;
1809 };
1810
1811 /*
1812 * Benchmarking
1813 */
1814 void radeon_benchmark(struct radeon_device *rdev, int test_number);
1815
1816
1817 /*
1818 * Testing
1819 */
1820 void radeon_test_moves(struct radeon_device *rdev);
1821 void radeon_test_ring_sync(struct radeon_device *rdev,
1822 struct radeon_ring *cpA,
1823 struct radeon_ring *cpB);
1824 void radeon_test_syncing(struct radeon_device *rdev);
1825
1826 /*
1827 * MMU Notifier
1828 */
1829 #if defined(CONFIG_MMU_NOTIFIER)
1830 int radeon_mn_register(struct radeon_bo *bo, unsigned long addr);
1831 void radeon_mn_unregister(struct radeon_bo *bo);
1832 #else
radeon_mn_register(struct radeon_bo * bo,unsigned long addr)1833 static inline int radeon_mn_register(struct radeon_bo *bo, unsigned long addr)
1834 {
1835 return -ENODEV;
1836 }
radeon_mn_unregister(struct radeon_bo * bo)1837 static inline void radeon_mn_unregister(struct radeon_bo *bo) {}
1838 #endif
1839
1840 /*
1841 * Debugfs
1842 */
1843 struct radeon_debugfs {
1844 struct drm_info_list *files;
1845 unsigned num_files;
1846 };
1847
1848 int radeon_debugfs_add_files(struct radeon_device *rdev,
1849 struct drm_info_list *files,
1850 unsigned nfiles);
1851 int radeon_debugfs_fence_init(struct radeon_device *rdev);
1852
1853 /*
1854 * ASIC ring specific functions.
1855 */
1856 struct radeon_asic_ring {
1857 /* ring read/write ptr handling */
1858 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1859 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1860 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1861
1862 /* validating and patching of IBs */
1863 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1864 int (*cs_parse)(struct radeon_cs_parser *p);
1865
1866 /* command emmit functions */
1867 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1868 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1869 void (*hdp_flush)(struct radeon_device *rdev, struct radeon_ring *ring);
1870 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
1871 struct radeon_semaphore *semaphore, bool emit_wait);
1872 void (*vm_flush)(struct radeon_device *rdev, struct radeon_ring *ring,
1873 unsigned vm_id, uint64_t pd_addr);
1874
1875 /* testing functions */
1876 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1877 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1878 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1879
1880 /* deprecated */
1881 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1882 };
1883
1884 /*
1885 * ASIC specific functions.
1886 */
1887 struct radeon_asic {
1888 int (*init)(struct radeon_device *rdev);
1889 void (*fini)(struct radeon_device *rdev);
1890 int (*resume)(struct radeon_device *rdev);
1891 int (*suspend)(struct radeon_device *rdev);
1892 void (*vga_set_state)(struct radeon_device *rdev, bool state);
1893 int (*asic_reset)(struct radeon_device *rdev, bool hard);
1894 /* Flush the HDP cache via MMIO */
1895 void (*mmio_hdp_flush)(struct radeon_device *rdev);
1896 /* check if 3D engine is idle */
1897 bool (*gui_idle)(struct radeon_device *rdev);
1898 /* wait for mc_idle */
1899 int (*mc_wait_for_idle)(struct radeon_device *rdev);
1900 /* get the reference clock */
1901 u32 (*get_xclk)(struct radeon_device *rdev);
1902 /* get the gpu clock counter */
1903 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
1904 /* get register for info ioctl */
1905 int (*get_allowed_info_register)(struct radeon_device *rdev, u32 reg, u32 *val);
1906 /* gart */
1907 struct {
1908 void (*tlb_flush)(struct radeon_device *rdev);
1909 uint64_t (*get_page_entry)(uint64_t addr, uint32_t flags);
1910 void (*set_page)(struct radeon_device *rdev, unsigned i,
1911 uint64_t entry);
1912 } gart;
1913 struct {
1914 int (*init)(struct radeon_device *rdev);
1915 void (*fini)(struct radeon_device *rdev);
1916 void (*copy_pages)(struct radeon_device *rdev,
1917 struct radeon_ib *ib,
1918 uint64_t pe, uint64_t src,
1919 unsigned count);
1920 void (*write_pages)(struct radeon_device *rdev,
1921 struct radeon_ib *ib,
1922 uint64_t pe,
1923 uint64_t addr, unsigned count,
1924 uint32_t incr, uint32_t flags);
1925 void (*set_pages)(struct radeon_device *rdev,
1926 struct radeon_ib *ib,
1927 uint64_t pe,
1928 uint64_t addr, unsigned count,
1929 uint32_t incr, uint32_t flags);
1930 void (*pad_ib)(struct radeon_ib *ib);
1931 } vm;
1932 /* ring specific callbacks */
1933 const struct radeon_asic_ring *ring[RADEON_NUM_RINGS];
1934 /* irqs */
1935 struct {
1936 int (*set)(struct radeon_device *rdev);
1937 int (*process)(struct radeon_device *rdev);
1938 } irq;
1939 /* displays */
1940 struct {
1941 /* display watermarks */
1942 void (*bandwidth_update)(struct radeon_device *rdev);
1943 /* get frame count */
1944 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1945 /* wait for vblank */
1946 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
1947 /* set backlight level */
1948 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
1949 /* get backlight level */
1950 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
1951 /* audio callbacks */
1952 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1953 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
1954 } display;
1955 /* copy functions for bo handling */
1956 struct {
1957 struct radeon_fence *(*blit)(struct radeon_device *rdev,
1958 uint64_t src_offset,
1959 uint64_t dst_offset,
1960 unsigned num_gpu_pages,
1961 struct dma_resv *resv);
1962 u32 blit_ring_index;
1963 struct radeon_fence *(*dma)(struct radeon_device *rdev,
1964 uint64_t src_offset,
1965 uint64_t dst_offset,
1966 unsigned num_gpu_pages,
1967 struct dma_resv *resv);
1968 u32 dma_ring_index;
1969 /* method used for bo copy */
1970 struct radeon_fence *(*copy)(struct radeon_device *rdev,
1971 uint64_t src_offset,
1972 uint64_t dst_offset,
1973 unsigned num_gpu_pages,
1974 struct dma_resv *resv);
1975 /* ring used for bo copies */
1976 u32 copy_ring_index;
1977 } copy;
1978 /* surfaces */
1979 struct {
1980 int (*set_reg)(struct radeon_device *rdev, int reg,
1981 uint32_t tiling_flags, uint32_t pitch,
1982 uint32_t offset, uint32_t obj_size);
1983 void (*clear_reg)(struct radeon_device *rdev, int reg);
1984 } surface;
1985 /* hotplug detect */
1986 struct {
1987 void (*init)(struct radeon_device *rdev);
1988 void (*fini)(struct radeon_device *rdev);
1989 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1990 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1991 } hpd;
1992 /* static power management */
1993 struct {
1994 void (*misc)(struct radeon_device *rdev);
1995 void (*prepare)(struct radeon_device *rdev);
1996 void (*finish)(struct radeon_device *rdev);
1997 void (*init_profile)(struct radeon_device *rdev);
1998 void (*get_dynpm_state)(struct radeon_device *rdev);
1999 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
2000 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
2001 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
2002 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
2003 int (*get_pcie_lanes)(struct radeon_device *rdev);
2004 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
2005 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
2006 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
2007 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk);
2008 int (*get_temperature)(struct radeon_device *rdev);
2009 } pm;
2010 /* dynamic power management */
2011 struct {
2012 int (*init)(struct radeon_device *rdev);
2013 void (*setup_asic)(struct radeon_device *rdev);
2014 int (*enable)(struct radeon_device *rdev);
2015 int (*late_enable)(struct radeon_device *rdev);
2016 void (*disable)(struct radeon_device *rdev);
2017 int (*pre_set_power_state)(struct radeon_device *rdev);
2018 int (*set_power_state)(struct radeon_device *rdev);
2019 void (*post_set_power_state)(struct radeon_device *rdev);
2020 void (*display_configuration_changed)(struct radeon_device *rdev);
2021 void (*fini)(struct radeon_device *rdev);
2022 u32 (*get_sclk)(struct radeon_device *rdev, bool low);
2023 u32 (*get_mclk)(struct radeon_device *rdev, bool low);
2024 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
2025 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m);
2026 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level);
2027 bool (*vblank_too_short)(struct radeon_device *rdev);
2028 void (*powergate_uvd)(struct radeon_device *rdev, bool gate);
2029 void (*enable_bapm)(struct radeon_device *rdev, bool enable);
2030 void (*fan_ctrl_set_mode)(struct radeon_device *rdev, u32 mode);
2031 u32 (*fan_ctrl_get_mode)(struct radeon_device *rdev);
2032 int (*set_fan_speed_percent)(struct radeon_device *rdev, u32 speed);
2033 int (*get_fan_speed_percent)(struct radeon_device *rdev, u32 *speed);
2034 u32 (*get_current_sclk)(struct radeon_device *rdev);
2035 u32 (*get_current_mclk)(struct radeon_device *rdev);
2036 } dpm;
2037 /* pageflipping */
2038 struct {
2039 void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base, bool async);
2040 bool (*page_flip_pending)(struct radeon_device *rdev, int crtc);
2041 } pflip;
2042 };
2043
2044 /*
2045 * Asic structures
2046 */
2047 struct r100_asic {
2048 const unsigned *reg_safe_bm;
2049 unsigned reg_safe_bm_size;
2050 u32 hdp_cntl;
2051 };
2052
2053 struct r300_asic {
2054 const unsigned *reg_safe_bm;
2055 unsigned reg_safe_bm_size;
2056 u32 resync_scratch;
2057 u32 hdp_cntl;
2058 };
2059
2060 struct r600_asic {
2061 unsigned max_pipes;
2062 unsigned max_tile_pipes;
2063 unsigned max_simds;
2064 unsigned max_backends;
2065 unsigned max_gprs;
2066 unsigned max_threads;
2067 unsigned max_stack_entries;
2068 unsigned max_hw_contexts;
2069 unsigned max_gs_threads;
2070 unsigned sx_max_export_size;
2071 unsigned sx_max_export_pos_size;
2072 unsigned sx_max_export_smx_size;
2073 unsigned sq_num_cf_insts;
2074 unsigned tiling_nbanks;
2075 unsigned tiling_npipes;
2076 unsigned tiling_group_size;
2077 unsigned tile_config;
2078 unsigned backend_map;
2079 unsigned active_simds;
2080 };
2081
2082 struct rv770_asic {
2083 unsigned max_pipes;
2084 unsigned max_tile_pipes;
2085 unsigned max_simds;
2086 unsigned max_backends;
2087 unsigned max_gprs;
2088 unsigned max_threads;
2089 unsigned max_stack_entries;
2090 unsigned max_hw_contexts;
2091 unsigned max_gs_threads;
2092 unsigned sx_max_export_size;
2093 unsigned sx_max_export_pos_size;
2094 unsigned sx_max_export_smx_size;
2095 unsigned sq_num_cf_insts;
2096 unsigned sx_num_of_sets;
2097 unsigned sc_prim_fifo_size;
2098 unsigned sc_hiz_tile_fifo_size;
2099 unsigned sc_earlyz_tile_fifo_fize;
2100 unsigned tiling_nbanks;
2101 unsigned tiling_npipes;
2102 unsigned tiling_group_size;
2103 unsigned tile_config;
2104 unsigned backend_map;
2105 unsigned active_simds;
2106 };
2107
2108 struct evergreen_asic {
2109 unsigned num_ses;
2110 unsigned max_pipes;
2111 unsigned max_tile_pipes;
2112 unsigned max_simds;
2113 unsigned max_backends;
2114 unsigned max_gprs;
2115 unsigned max_threads;
2116 unsigned max_stack_entries;
2117 unsigned max_hw_contexts;
2118 unsigned max_gs_threads;
2119 unsigned sx_max_export_size;
2120 unsigned sx_max_export_pos_size;
2121 unsigned sx_max_export_smx_size;
2122 unsigned sq_num_cf_insts;
2123 unsigned sx_num_of_sets;
2124 unsigned sc_prim_fifo_size;
2125 unsigned sc_hiz_tile_fifo_size;
2126 unsigned sc_earlyz_tile_fifo_size;
2127 unsigned tiling_nbanks;
2128 unsigned tiling_npipes;
2129 unsigned tiling_group_size;
2130 unsigned tile_config;
2131 unsigned backend_map;
2132 unsigned active_simds;
2133 };
2134
2135 struct cayman_asic {
2136 unsigned max_shader_engines;
2137 unsigned max_pipes_per_simd;
2138 unsigned max_tile_pipes;
2139 unsigned max_simds_per_se;
2140 unsigned max_backends_per_se;
2141 unsigned max_texture_channel_caches;
2142 unsigned max_gprs;
2143 unsigned max_threads;
2144 unsigned max_gs_threads;
2145 unsigned max_stack_entries;
2146 unsigned sx_num_of_sets;
2147 unsigned sx_max_export_size;
2148 unsigned sx_max_export_pos_size;
2149 unsigned sx_max_export_smx_size;
2150 unsigned max_hw_contexts;
2151 unsigned sq_num_cf_insts;
2152 unsigned sc_prim_fifo_size;
2153 unsigned sc_hiz_tile_fifo_size;
2154 unsigned sc_earlyz_tile_fifo_size;
2155
2156 unsigned num_shader_engines;
2157 unsigned num_shader_pipes_per_simd;
2158 unsigned num_tile_pipes;
2159 unsigned num_simds_per_se;
2160 unsigned num_backends_per_se;
2161 unsigned backend_disable_mask_per_asic;
2162 unsigned backend_map;
2163 unsigned num_texture_channel_caches;
2164 unsigned mem_max_burst_length_bytes;
2165 unsigned mem_row_size_in_kb;
2166 unsigned shader_engine_tile_size;
2167 unsigned num_gpus;
2168 unsigned multi_gpu_tile_size;
2169
2170 unsigned tile_config;
2171 unsigned active_simds;
2172 };
2173
2174 struct si_asic {
2175 unsigned max_shader_engines;
2176 unsigned max_tile_pipes;
2177 unsigned max_cu_per_sh;
2178 unsigned max_sh_per_se;
2179 unsigned max_backends_per_se;
2180 unsigned max_texture_channel_caches;
2181 unsigned max_gprs;
2182 unsigned max_gs_threads;
2183 unsigned max_hw_contexts;
2184 unsigned sc_prim_fifo_size_frontend;
2185 unsigned sc_prim_fifo_size_backend;
2186 unsigned sc_hiz_tile_fifo_size;
2187 unsigned sc_earlyz_tile_fifo_size;
2188
2189 unsigned num_tile_pipes;
2190 unsigned backend_enable_mask;
2191 unsigned backend_disable_mask_per_asic;
2192 unsigned backend_map;
2193 unsigned num_texture_channel_caches;
2194 unsigned mem_max_burst_length_bytes;
2195 unsigned mem_row_size_in_kb;
2196 unsigned shader_engine_tile_size;
2197 unsigned num_gpus;
2198 unsigned multi_gpu_tile_size;
2199
2200 unsigned tile_config;
2201 uint32_t tile_mode_array[32];
2202 uint32_t active_cus;
2203 };
2204
2205 struct cik_asic {
2206 unsigned max_shader_engines;
2207 unsigned max_tile_pipes;
2208 unsigned max_cu_per_sh;
2209 unsigned max_sh_per_se;
2210 unsigned max_backends_per_se;
2211 unsigned max_texture_channel_caches;
2212 unsigned max_gprs;
2213 unsigned max_gs_threads;
2214 unsigned max_hw_contexts;
2215 unsigned sc_prim_fifo_size_frontend;
2216 unsigned sc_prim_fifo_size_backend;
2217 unsigned sc_hiz_tile_fifo_size;
2218 unsigned sc_earlyz_tile_fifo_size;
2219
2220 unsigned num_tile_pipes;
2221 unsigned backend_enable_mask;
2222 unsigned backend_disable_mask_per_asic;
2223 unsigned backend_map;
2224 unsigned num_texture_channel_caches;
2225 unsigned mem_max_burst_length_bytes;
2226 unsigned mem_row_size_in_kb;
2227 unsigned shader_engine_tile_size;
2228 unsigned num_gpus;
2229 unsigned multi_gpu_tile_size;
2230
2231 unsigned tile_config;
2232 uint32_t tile_mode_array[32];
2233 uint32_t macrotile_mode_array[16];
2234 uint32_t active_cus;
2235 };
2236
2237 union radeon_asic_config {
2238 struct r300_asic r300;
2239 struct r100_asic r100;
2240 struct r600_asic r600;
2241 struct rv770_asic rv770;
2242 struct evergreen_asic evergreen;
2243 struct cayman_asic cayman;
2244 struct si_asic si;
2245 struct cik_asic cik;
2246 };
2247
2248 /*
2249 * asic initizalization from radeon_asic.c
2250 */
2251 void radeon_agp_disable(struct radeon_device *rdev);
2252 int radeon_asic_init(struct radeon_device *rdev);
2253
2254
2255 /*
2256 * IOCTL.
2257 */
2258 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
2259 struct drm_file *filp);
2260 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
2261 struct drm_file *filp);
2262 int radeon_gem_userptr_ioctl(struct drm_device *dev, void *data,
2263 struct drm_file *filp);
2264 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
2265 struct drm_file *file_priv);
2266 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
2267 struct drm_file *file_priv);
2268 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2269 struct drm_file *file_priv);
2270 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
2271 struct drm_file *file_priv);
2272 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2273 struct drm_file *filp);
2274 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
2275 struct drm_file *filp);
2276 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
2277 struct drm_file *filp);
2278 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
2279 struct drm_file *filp);
2280 int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
2281 struct drm_file *filp);
2282 int radeon_gem_op_ioctl(struct drm_device *dev, void *data,
2283 struct drm_file *filp);
2284 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
2285 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
2286 struct drm_file *filp);
2287 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
2288 struct drm_file *filp);
2289
2290 /* VRAM scratch page for HDP bug, default vram page */
2291 struct r600_vram_scratch {
2292 struct radeon_bo *robj;
2293 volatile uint32_t *ptr;
2294 u64 gpu_addr;
2295 };
2296
2297 /*
2298 * ACPI
2299 */
2300 struct radeon_atif_notification_cfg {
2301 bool enabled;
2302 int command_code;
2303 };
2304
2305 struct radeon_atif_notifications {
2306 bool display_switch;
2307 bool expansion_mode_change;
2308 bool thermal_state;
2309 bool forced_power_state;
2310 bool system_power_state;
2311 bool display_conf_change;
2312 bool px_gfx_switch;
2313 bool brightness_change;
2314 bool dgpu_display_event;
2315 };
2316
2317 struct radeon_atif_functions {
2318 bool system_params;
2319 bool sbios_requests;
2320 bool select_active_disp;
2321 bool lid_state;
2322 bool get_tv_standard;
2323 bool set_tv_standard;
2324 bool get_panel_expansion_mode;
2325 bool set_panel_expansion_mode;
2326 bool temperature_change;
2327 bool graphics_device_types;
2328 };
2329
2330 struct radeon_atif {
2331 struct radeon_atif_notifications notifications;
2332 struct radeon_atif_functions functions;
2333 struct radeon_atif_notification_cfg notification_cfg;
2334 struct radeon_encoder *encoder_for_bl;
2335 };
2336
2337 struct radeon_atcs_functions {
2338 bool get_ext_state;
2339 bool pcie_perf_req;
2340 bool pcie_dev_rdy;
2341 bool pcie_bus_width;
2342 };
2343
2344 struct radeon_atcs {
2345 struct radeon_atcs_functions functions;
2346 };
2347
2348 /*
2349 * Core structure, functions and helpers.
2350 */
2351 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
2352 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
2353
2354 struct radeon_device {
2355 struct device *dev;
2356 struct drm_device *ddev;
2357 struct pci_dev *pdev;
2358 struct rw_semaphore exclusive_lock;
2359 /* ASIC */
2360 union radeon_asic_config config;
2361 enum radeon_family family;
2362 unsigned long flags;
2363 int usec_timeout;
2364 enum radeon_pll_errata pll_errata;
2365 int num_gb_pipes;
2366 int num_z_pipes;
2367 int disp_priority;
2368 /* BIOS */
2369 uint8_t *bios;
2370 bool is_atom_bios;
2371 uint16_t bios_header_start;
2372 struct radeon_bo *stolen_vga_memory;
2373 /* Register mmio */
2374 #ifndef __NetBSD__
2375 resource_size_t rmmio_base;
2376 resource_size_t rmmio_size;
2377 #endif
2378 /* protects concurrent MM_INDEX/DATA based register access */
2379 spinlock_t mmio_idx_lock;
2380 /* protects concurrent SMC based register access */
2381 spinlock_t smc_idx_lock;
2382 /* protects concurrent PLL register access */
2383 spinlock_t pll_idx_lock;
2384 /* protects concurrent MC register access */
2385 spinlock_t mc_idx_lock;
2386 /* protects concurrent PCIE register access */
2387 spinlock_t pcie_idx_lock;
2388 /* protects concurrent PCIE_PORT register access */
2389 spinlock_t pciep_idx_lock;
2390 /* protects concurrent PIF register access */
2391 spinlock_t pif_idx_lock;
2392 /* protects concurrent CG register access */
2393 spinlock_t cg_idx_lock;
2394 /* protects concurrent UVD register access */
2395 spinlock_t uvd_idx_lock;
2396 /* protects concurrent RCU register access */
2397 spinlock_t rcu_idx_lock;
2398 /* protects concurrent DIDT register access */
2399 spinlock_t didt_idx_lock;
2400 /* protects concurrent ENDPOINT (audio) register access */
2401 spinlock_t end_idx_lock;
2402 #ifdef __NetBSD__
2403 bus_space_tag_t rmmio_bst;
2404 bus_space_handle_t rmmio_bsh;
2405 bus_addr_t rmmio_addr;
2406 bus_size_t rmmio_size;
2407 #else
2408 void __iomem *rmmio;
2409 #endif
2410 radeon_rreg_t mc_rreg;
2411 radeon_wreg_t mc_wreg;
2412 radeon_rreg_t pll_rreg;
2413 radeon_wreg_t pll_wreg;
2414 uint32_t pcie_reg_mask;
2415 radeon_rreg_t pciep_rreg;
2416 radeon_wreg_t pciep_wreg;
2417 /* io port */
2418 #ifdef __NetBSD__
2419 bus_space_tag_t rio_mem_bst;
2420 bus_space_handle_t rio_mem_bsh;
2421 bus_size_t rio_mem_size;
2422 #else
2423 void __iomem *rio_mem;
2424 resource_size_t rio_mem_size;
2425 #endif
2426 struct radeon_clock clock;
2427 struct radeon_mc mc;
2428 struct radeon_gart gart;
2429 struct radeon_mode_info mode_info;
2430 struct radeon_scratch scratch;
2431 struct radeon_doorbell doorbell;
2432 struct radeon_mman mman;
2433 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
2434 spinlock_t fence_lock;
2435 drm_waitqueue_t fence_queue;
2436 TAILQ_HEAD(, radeon_fence) fence_check;
2437 u64 fence_context;
2438 struct mutex ring_lock;
2439 struct radeon_ring ring[RADEON_NUM_RINGS];
2440 bool ib_pool_ready;
2441 struct radeon_sa_manager ring_tmp_bo;
2442 struct radeon_irq irq;
2443 struct radeon_asic *asic;
2444 struct radeon_gem gem;
2445 struct radeon_pm pm;
2446 struct radeon_uvd uvd;
2447 struct radeon_vce vce;
2448 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
2449 struct radeon_wb wb;
2450 struct radeon_dummy_page dummy_page;
2451 bool shutdown;
2452 bool need_swiotlb;
2453 bool accel_working;
2454 bool fastfb_working; /* IGP feature*/
2455 bool needs_reset, in_reset;
2456 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
2457 const struct firmware *me_fw; /* all family ME firmware */
2458 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
2459 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
2460 const struct firmware *mc_fw; /* NI MC firmware */
2461 const struct firmware *ce_fw; /* SI CE firmware */
2462 const struct firmware *mec_fw; /* CIK MEC firmware */
2463 const struct firmware *mec2_fw; /* KV MEC2 firmware */
2464 const struct firmware *sdma_fw; /* CIK SDMA firmware */
2465 const struct firmware *smc_fw; /* SMC firmware */
2466 const struct firmware *uvd_fw; /* UVD firmware */
2467 const struct firmware *vce_fw; /* VCE firmware */
2468 bool new_fw;
2469 struct r600_vram_scratch vram_scratch;
2470 int msi_enabled; /* msi enabled */
2471 struct r600_ih ih; /* r6/700 interrupt ring */
2472 struct radeon_rlc rlc;
2473 struct radeon_mec mec;
2474 struct delayed_work hotplug_work;
2475 struct work_struct dp_work;
2476 struct work_struct audio_work;
2477 int num_crtc; /* number of crtcs */
2478 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
2479 bool has_uvd;
2480 bool has_vce;
2481 struct r600_audio audio; /* audio stuff */
2482 struct notifier_block acpi_nb;
2483 /* only one userspace can use Hyperz features or CMASK at a time */
2484 struct drm_file *hyperz_filp;
2485 struct drm_file *cmask_filp;
2486 /* i2c buses */
2487 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
2488 /* debugfs */
2489 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
2490 unsigned debugfs_count;
2491 /* virtual memory */
2492 struct radeon_vm_manager vm_manager;
2493 struct mutex gpu_clock_mutex;
2494 /* memory stats */
2495 atomic64_t vram_usage;
2496 atomic64_t gtt_usage;
2497 atomic64_t num_bytes_moved;
2498 atomic_t gpu_reset_counter;
2499 /* ACPI interface */
2500 struct radeon_atif atif;
2501 struct radeon_atcs atcs;
2502 /* srbm instance registers */
2503 struct mutex srbm_mutex;
2504 /* clock, powergating flags */
2505 u32 cg_flags;
2506 u32 pg_flags;
2507
2508 struct dev_pm_domain vga_pm_domain;
2509 bool have_disp_power_ref;
2510 u32 px_quirk_flags;
2511
2512 /* tracking pinned memory */
2513 u64 vram_pin_size;
2514 u64 gart_pin_size;
2515 };
2516
2517 bool radeon_is_px(struct drm_device *dev);
2518 int radeon_device_init(struct radeon_device *rdev,
2519 struct drm_device *ddev,
2520 struct pci_dev *pdev,
2521 uint32_t flags);
2522 void radeon_device_fini(struct radeon_device *rdev);
2523 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
2524
2525 #define RADEON_MIN_MMIO_SIZE 0x10000
2526
2527 uint32_t r100_mm_rreg_slow(struct radeon_device *rdev, uint32_t reg);
2528 void r100_mm_wreg_slow(struct radeon_device *rdev, uint32_t reg, uint32_t v);
r100_mm_rreg(struct radeon_device * rdev,uint32_t reg,bool always_indirect)2529 static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
2530 bool always_indirect)
2531 {
2532 /* The mmio size is 64kb at minimum. Allows the if to be optimized out. */
2533 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2534 #ifdef __NetBSD__
2535 return bus_space_read_4(rdev->rmmio_bst, rdev->rmmio_bsh, reg);
2536 #else
2537 return readl(((void __iomem *)rdev->rmmio) + reg);
2538 #endif
2539 else
2540 return r100_mm_rreg_slow(rdev, reg);
2541 }
r100_mm_wreg(struct radeon_device * rdev,uint32_t reg,uint32_t v,bool always_indirect)2542 static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
2543 bool always_indirect)
2544 {
2545 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2546 #ifdef __NetBSD__
2547 bus_space_write_4(rdev->rmmio_bst, rdev->rmmio_bsh, reg, v);
2548 #else
2549 writel(v, ((void __iomem *)rdev->rmmio) + reg);
2550 #endif
2551 else
2552 r100_mm_wreg_slow(rdev, reg, v);
2553 }
2554
2555 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
2556 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2557
2558 u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index);
2559 void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v);
2560
2561 /*
2562 * Cast helper
2563 */
2564 extern const struct dma_fence_ops radeon_fence_ops;
2565
to_radeon_fence(struct dma_fence * f)2566 static inline struct radeon_fence *to_radeon_fence(struct dma_fence *f)
2567 {
2568 struct radeon_fence *__f = container_of(f, struct radeon_fence, base);
2569
2570 if (__f->base.ops == &radeon_fence_ops)
2571 return __f;
2572
2573 return NULL;
2574 }
2575
2576 /*
2577 * Registers read & write functions.
2578 */
2579 #ifdef __NetBSD__
2580 #define RREG8(r) bus_space_read_1(rdev->rmmio_bst, rdev->rmmio_bsh, (r))
2581 #define WREG8(r, v) bus_space_write_1(rdev->rmmio_bst, rdev->rmmio_bsh, (r), (v))
2582 #define RREG16(r) bus_space_read_2(rdev->rmmio_bst, rdev->rmmio_bsh, (r))
2583 #define WREG16(r, v) bus_space_write_2(rdev->rmmio_bst, rdev->rmmio_bsh, (r), (v))
2584 #else
2585 #define RREG8(reg) readb((rdev->rmmio) + (reg))
2586 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
2587 #define RREG16(reg) readw((rdev->rmmio) + (reg))
2588 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
2589 #endif
2590 #define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
2591 #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
2592 #define DREG32(reg) pr_info("REGISTER: " #reg " : 0x%08X\n", \
2593 r100_mm_rreg(rdev, (reg), false))
2594 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
2595 #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
2596 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2597 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2598 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
2599 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
2600 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
2601 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
2602 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
2603 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
2604 #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
2605 #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
2606 #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
2607 #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
2608 #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
2609 #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
2610 #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
2611 #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
2612 #define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
2613 #define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
2614 #define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
2615 #define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
2616 #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
2617 #define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
2618 #define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg))
2619 #define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v))
2620 #define WREG32_P(reg, val, mask) \
2621 do { \
2622 uint32_t tmp_ = RREG32(reg); \
2623 tmp_ &= (mask); \
2624 tmp_ |= ((val) & ~(mask)); \
2625 WREG32(reg, tmp_); \
2626 } while (0)
2627 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2628 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2629 #define WREG32_PLL_P(reg, val, mask) \
2630 do { \
2631 uint32_t tmp_ = RREG32_PLL(reg); \
2632 tmp_ &= (mask); \
2633 tmp_ |= ((val) & ~(mask)); \
2634 WREG32_PLL(reg, tmp_); \
2635 } while (0)
2636 #define WREG32_SMC_P(reg, val, mask) \
2637 do { \
2638 uint32_t tmp_ = RREG32_SMC(reg); \
2639 tmp_ &= (mask); \
2640 tmp_ |= ((val) & ~(mask)); \
2641 WREG32_SMC(reg, tmp_); \
2642 } while (0)
2643 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
2644 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
2645 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
2646
2647 #define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index))
2648 #define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v))
2649
2650 /*
2651 * Indirect registers accessors.
2652 * They used to be inlined, but this increases code size by ~65 kbytes.
2653 * Since each performs a pair of MMIO ops
2654 * within a spin_lock_irqsave/spin_unlock_irqrestore region,
2655 * the cost of call+ret is almost negligible. MMIO and locking
2656 * costs several dozens of cycles each at best, call+ret is ~5 cycles.
2657 */
2658 uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg);
2659 void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
2660 u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg);
2661 void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2662 u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg);
2663 void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2664 u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg);
2665 void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2666 u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg);
2667 void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2668 u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg);
2669 void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2670 u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg);
2671 void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2672 u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg);
2673 void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2674
2675 void r100_pll_errata_after_index(struct radeon_device *rdev);
2676
2677
2678 /*
2679 * ASICs helpers.
2680 */
2681 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
2682 (rdev->pdev->device == 0x5969))
2683 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
2684 (rdev->family == CHIP_RV200) || \
2685 (rdev->family == CHIP_RS100) || \
2686 (rdev->family == CHIP_RS200) || \
2687 (rdev->family == CHIP_RV250) || \
2688 (rdev->family == CHIP_RV280) || \
2689 (rdev->family == CHIP_RS300))
2690 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
2691 (rdev->family == CHIP_RV350) || \
2692 (rdev->family == CHIP_R350) || \
2693 (rdev->family == CHIP_RV380) || \
2694 (rdev->family == CHIP_R420) || \
2695 (rdev->family == CHIP_R423) || \
2696 (rdev->family == CHIP_RV410) || \
2697 (rdev->family == CHIP_RS400) || \
2698 (rdev->family == CHIP_RS480))
2699 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
2700 (rdev->ddev->pdev->device == 0x9443) || \
2701 (rdev->ddev->pdev->device == 0x944B) || \
2702 (rdev->ddev->pdev->device == 0x9506) || \
2703 (rdev->ddev->pdev->device == 0x9509) || \
2704 (rdev->ddev->pdev->device == 0x950F) || \
2705 (rdev->ddev->pdev->device == 0x689C) || \
2706 (rdev->ddev->pdev->device == 0x689D))
2707 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
2708 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
2709 (rdev->family == CHIP_RS690) || \
2710 (rdev->family == CHIP_RS740) || \
2711 (rdev->family >= CHIP_R600))
2712 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
2713 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
2714 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
2715 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
2716 (rdev->flags & RADEON_IS_IGP))
2717 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
2718 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
2719 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
2720 (rdev->flags & RADEON_IS_IGP))
2721 #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
2722 #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
2723 #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
2724 #define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI))
2725 #define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE))
2726 #define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \
2727 (rdev->family == CHIP_MULLINS))
2728
2729 #define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \
2730 (rdev->ddev->pdev->device == 0x6850) || \
2731 (rdev->ddev->pdev->device == 0x6858) || \
2732 (rdev->ddev->pdev->device == 0x6859) || \
2733 (rdev->ddev->pdev->device == 0x6840) || \
2734 (rdev->ddev->pdev->device == 0x6841) || \
2735 (rdev->ddev->pdev->device == 0x6842) || \
2736 (rdev->ddev->pdev->device == 0x6843))
2737
2738 /*
2739 * BIOS helpers.
2740 */
2741 #define RBIOS8(i) (rdev->bios[i])
2742 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2743 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2744
2745 int radeon_combios_init(struct radeon_device *rdev);
2746 void radeon_combios_fini(struct radeon_device *rdev);
2747 int radeon_atombios_init(struct radeon_device *rdev);
2748 void radeon_atombios_fini(struct radeon_device *rdev);
2749
2750
2751 /*
2752 * RING helpers.
2753 */
2754
2755 /**
2756 * radeon_ring_write - write a value to the ring
2757 *
2758 * @ring: radeon_ring structure holding ring information
2759 * @v: dword (dw) value to write
2760 *
2761 * Write a value to the requested ring buffer (all asics).
2762 */
radeon_ring_write(struct radeon_ring * ring,uint32_t v)2763 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
2764 {
2765 if (ring->count_dw <= 0)
2766 DRM_ERROR("radeon: writing more dwords to the ring than expected!\n");
2767
2768 ring->ring[ring->wptr++] = v;
2769 ring->wptr &= ring->ptr_mask;
2770 ring->count_dw--;
2771 ring->ring_free_dw--;
2772 }
2773
2774 /*
2775 * ASICs macro.
2776 */
2777 #define radeon_init(rdev) (rdev)->asic->init((rdev))
2778 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2779 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2780 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
2781 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p))
2782 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
2783 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev), false)
2784 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
2785 #define radeon_gart_get_page_entry(a, f) (rdev)->asic->gart.get_page_entry((a), (f))
2786 #define radeon_gart_set_page(rdev, i, e) (rdev)->asic->gart.set_page((rdev), (i), (e))
2787 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2788 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
2789 #define radeon_asic_vm_copy_pages(rdev, ib, pe, src, count) ((rdev)->asic->vm.copy_pages((rdev), (ib), (pe), (src), (count)))
2790 #define radeon_asic_vm_write_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.write_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2791 #define radeon_asic_vm_set_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2792 #define radeon_asic_vm_pad_ib(rdev, ib) ((rdev)->asic->vm.pad_ib((ib)))
2793 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp))
2794 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp))
2795 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp))
2796 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))
2797 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))
2798 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))
2799 #define radeon_ring_vm_flush(rdev, r, vm_id, pd_addr) (rdev)->asic->ring[(r)->idx]->vm_flush((rdev), (r), (vm_id), (pd_addr))
2800 #define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))
2801 #define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
2802 #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
2803 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2804 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
2805 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
2806 #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
2807 #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
2808 #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2809 #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
2810 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence))
2811 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
2812 #define radeon_copy_blit(rdev, s, d, np, resv) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (resv))
2813 #define radeon_copy_dma(rdev, s, d, np, resv) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (resv))
2814 #define radeon_copy(rdev, s, d, np, resv) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (resv))
2815 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2816 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2817 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
2818 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2819 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2820 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2821 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2822 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
2823 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
2824 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
2825 #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
2826 #define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec))
2827 #define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
2828 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
2829 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
2830 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
2831 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
2832 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
2833 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
2834 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
2835 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
2836 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
2837 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
2838 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
2839 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
2840 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
2841 #define radeon_page_flip(rdev, crtc, base, async) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base), (async))
2842 #define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc))
2843 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
2844 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
2845 #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
2846 #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
2847 #define radeon_get_allowed_info_register(rdev, r, v) (rdev)->asic->get_allowed_info_register((rdev), (r), (v))
2848 #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2849 #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2850 #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
2851 #define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev))
2852 #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
2853 #define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
2854 #define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
2855 #define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
2856 #define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
2857 #define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
2858 #define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
2859 #define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
2860 #define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
2861 #define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
2862 #define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l))
2863 #define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
2864 #define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g))
2865 #define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e))
2866 #define radeon_dpm_get_current_sclk(rdev) rdev->asic->dpm.get_current_sclk((rdev))
2867 #define radeon_dpm_get_current_mclk(rdev) rdev->asic->dpm.get_current_mclk((rdev))
2868
2869 /* Common functions */
2870 /* AGP */
2871 extern int radeon_gpu_reset(struct radeon_device *rdev);
2872 extern void radeon_pci_config_reset(struct radeon_device *rdev);
2873 extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
2874 extern void radeon_agp_disable(struct radeon_device *rdev);
2875 extern int radeon_modeset_init(struct radeon_device *rdev);
2876 extern void radeon_modeset_fini(struct radeon_device *rdev);
2877 extern bool radeon_card_posted(struct radeon_device *rdev);
2878 extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
2879 extern void radeon_update_display_priority(struct radeon_device *rdev);
2880 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
2881 extern void radeon_scratch_init(struct radeon_device *rdev);
2882 extern void radeon_wb_fini(struct radeon_device *rdev);
2883 extern int radeon_wb_init(struct radeon_device *rdev);
2884 extern void radeon_wb_disable(struct radeon_device *rdev);
2885 extern void radeon_surface_init(struct radeon_device *rdev);
2886 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
2887 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
2888 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
2889 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
2890 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
2891 extern int radeon_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
2892 uint32_t flags);
2893 extern bool radeon_ttm_tt_has_userptr(struct ttm_tt *ttm);
2894 extern bool radeon_ttm_tt_is_readonly(struct ttm_tt *ttm);
2895 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2896 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
2897 extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2898 extern int radeon_suspend_kms(struct drm_device *dev, bool suspend,
2899 bool fbcon, bool freeze);
2900 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
2901 extern void radeon_program_register_sequence(struct radeon_device *rdev,
2902 const u32 *registers,
2903 const u32 array_size);
2904
2905 /*
2906 * vm
2907 */
2908 int radeon_vm_manager_init(struct radeon_device *rdev);
2909 void radeon_vm_manager_fini(struct radeon_device *rdev);
2910 int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
2911 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
2912 struct radeon_bo_list *radeon_vm_get_bos(struct radeon_device *rdev,
2913 struct radeon_vm *vm,
2914 struct list_head *head);
2915 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
2916 struct radeon_vm *vm, int ring);
2917 void radeon_vm_flush(struct radeon_device *rdev,
2918 struct radeon_vm *vm,
2919 int ring, struct radeon_fence *fence);
2920 void radeon_vm_fence(struct radeon_device *rdev,
2921 struct radeon_vm *vm,
2922 struct radeon_fence *fence);
2923 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
2924 int radeon_vm_update_page_directory(struct radeon_device *rdev,
2925 struct radeon_vm *vm);
2926 int radeon_vm_clear_freed(struct radeon_device *rdev,
2927 struct radeon_vm *vm);
2928 int radeon_vm_clear_invalids(struct radeon_device *rdev,
2929 struct radeon_vm *vm);
2930 int radeon_vm_bo_update(struct radeon_device *rdev,
2931 struct radeon_bo_va *bo_va,
2932 struct ttm_mem_reg *mem);
2933 void radeon_vm_bo_invalidate(struct radeon_device *rdev,
2934 struct radeon_bo *bo);
2935 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
2936 struct radeon_bo *bo);
2937 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
2938 struct radeon_vm *vm,
2939 struct radeon_bo *bo);
2940 int radeon_vm_bo_set_addr(struct radeon_device *rdev,
2941 struct radeon_bo_va *bo_va,
2942 uint64_t offset,
2943 uint32_t flags);
2944 void radeon_vm_bo_rmv(struct radeon_device *rdev,
2945 struct radeon_bo_va *bo_va);
2946
2947 /* audio */
2948 void r600_audio_update_hdmi(struct work_struct *work);
2949 struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev);
2950 struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev);
2951 void r600_audio_enable(struct radeon_device *rdev,
2952 struct r600_audio_pin *pin,
2953 u8 enable_mask);
2954 void dce6_audio_enable(struct radeon_device *rdev,
2955 struct r600_audio_pin *pin,
2956 u8 enable_mask);
2957
2958 /*
2959 * R600 vram scratch functions
2960 */
2961 int r600_vram_scratch_init(struct radeon_device *rdev);
2962 void r600_vram_scratch_fini(struct radeon_device *rdev);
2963
2964 /*
2965 * r600 cs checking helper
2966 */
2967 unsigned r600_mip_minify(unsigned size, unsigned level);
2968 bool r600_fmt_is_valid_color(u32 format);
2969 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
2970 int r600_fmt_get_blocksize(u32 format);
2971 int r600_fmt_get_nblocksx(u32 format, u32 w);
2972 int r600_fmt_get_nblocksy(u32 format, u32 h);
2973
2974 /*
2975 * r600 functions used by radeon_encoder.c
2976 */
2977 struct radeon_hdmi_acr {
2978 u32 clock;
2979
2980 int n_32khz;
2981 int cts_32khz;
2982
2983 int n_44_1khz;
2984 int cts_44_1khz;
2985
2986 int n_48khz;
2987 int cts_48khz;
2988
2989 };
2990
2991 extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
2992
2993 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
2994 u32 tiling_pipe_num,
2995 u32 max_rb_num,
2996 u32 total_max_rb_num,
2997 u32 enabled_rb_mask);
2998
2999 /*
3000 * evergreen functions used by radeon_encoder.c
3001 */
3002
3003 extern int ni_init_microcode(struct radeon_device *rdev);
3004 extern int ni_mc_load_microcode(struct radeon_device *rdev);
3005
3006 /* radeon_acpi.c */
3007 #if defined(CONFIG_ACPI)
3008 extern int radeon_acpi_init(struct radeon_device *rdev);
3009 extern void radeon_acpi_fini(struct radeon_device *rdev);
3010 extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev);
3011 extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev,
3012 u8 perf_req, bool advertise);
3013 extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev);
3014 #else
radeon_acpi_init(struct radeon_device * rdev)3015 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
radeon_acpi_fini(struct radeon_device * rdev)3016 static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
3017 #endif
3018
3019 int radeon_cs_packet_parse(struct radeon_cs_parser *p,
3020 struct radeon_cs_packet *pkt,
3021 unsigned idx);
3022 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
3023 void radeon_cs_dump_packet(struct radeon_cs_parser *p,
3024 struct radeon_cs_packet *pkt);
3025 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
3026 struct radeon_bo_list **cs_reloc,
3027 int nomm);
3028 int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
3029 uint32_t *vline_start_end,
3030 uint32_t *vline_status);
3031
3032 /* interrupt control register helpers */
3033 void radeon_irq_kms_set_irq_n_enabled(struct radeon_device *rdev,
3034 u32 reg, u32 mask,
3035 bool enable, const char *name,
3036 unsigned n);
3037
3038 #include "radeon_object.h"
3039
3040 #endif
3041