| /netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | ResourcePriorityQueue.cpp | 60 RegPressure.resize(NumRC); in ResourcePriorityQueue()
62 std::fill(RegPressure.begin(), RegPressure.end(), 0); in ResourcePriorityQueue()
369 if ((RegPressure[RC->getID()] + in regPressureDelta()
371 (RegPressure[RC->getID()] + in regPressureDelta()
484 RegPressure[RC->getID()] += numberRCValSuccInSU(SU, RC->getID()); in scheduledNode()
495 if (RegPressure[RC->getID()] > in scheduledNode()
497 RegPressure[RC->getID()] -= numberRCValPredInSU(SU, RC->getID()); in scheduledNode()
498 else RegPressure[RC->getID()] = 0; in scheduledNode()
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| H A D | ScheduleDAGRRList.cpp | 1745 std::vector<unsigned> RegPressure; member in __anon0fc5070f0311::RegReductionPQBase
1764 RegPressure.resize(NumRC); in RegReductionPQBase()
1766 std::fill(RegPressure.begin(), RegPressure.end(), 0); in RegReductionPQBase()
1789 std::fill(RegPressure.begin(), RegPressure.end(), 0); in releaseState()
2078 unsigned RP = RegPressure[Id]; in dumpRegPressure()
2123 if (RegPressure[RCId] >= RegLimit[RCId]) in MayReduceRegPressure()
2215 RegPressure[RCId] += Cost; in scheduledNode()
2230 if (RegPressure[RCId] < Cost) { in scheduledNode()
2235 RegPressure[RCId] = 0; in scheduledNode()
2238 RegPressure[RCId] -= Cost; in scheduledNode()
[all …]
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| H A D | SelectionDAGISel.cpp | 267 if (TLI->getSchedulingPreference() == Sched::RegPressure) in createDefaultScheduler()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | MachineLICM.cpp | 145 SmallVector<unsigned, 8> RegPressure; member in __anon91fb95ef0111::MachineLICMBase
186 RegPressure.clear(); in releaseMemory()
353 RegPressure.resize(NumRPS); in runOnMachineFunction()
354 std::fill(RegPressure.begin(), RegPressure.end(), 0); in runOnMachineFunction()
666 BackTrace.push_back(RegPressure); in EnterScope()
788 std::fill(RegPressure.begin(), RegPressure.end(), 0); in InitRegPressure()
811 if (static_cast<int>(RegPressure[Class]) < -RPIdAndCost.second) in UpdateRegPressure()
812 RegPressure[Class] = 0; in UpdateRegPressure()
814 RegPressure[Class] += RPIdAndCost.second; in UpdateRegPressure()
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| /netbsd/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | ResourcePriorityQueue.h | 52 std::vector<unsigned> RegPressure; variable
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| H A D | MachineScheduler.h | 407 IntervalPressure RegPressure; variable
431 RegClassInfo(C->RegClassInfo), RPTracker(RegPressure), in ScheduleDAGMILive()
451 const IntervalPressure &getRegPressure() const { return RegPressure; } in getRegPressure()
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| H A D | TargetLowering.h | 100 RegPressure, // Scheduling for lowest register pressure. enumerator
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.cpp | 47 setSchedulingPreference(Sched::RegPressure); in AVRTargetLowering()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 52 setSchedulingPreference(Sched::RegPressure); in WebAssemblyTargetLowering()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 351 setSchedulingPreference(Sched::RegPressure); in NVPTXTargetLowering()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 1532 setSchedulingPreference(Sched::RegPressure); in ARMTargetLowering()
1869 return Sched::RegPressure; in getSchedulingPreference()
1880 return Sched::RegPressure; in getSchedulingPreference()
1888 return Sched::RegPressure; in getSchedulingPreference()
1893 return Sched::RegPressure; in getSchedulingPreference()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 512 setSchedulingPreference(Sched::RegPressure); in AMDGPUTargetLowering()
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| H A D | SIISelLowering.cpp | 851 setSchedulingPreference(Sched::RegPressure); in SITargetLowering()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 124 setSchedulingPreference(Sched::RegPressure); in SystemZTargetLowering()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 136 setSchedulingPreference(Sched::RegPressure); in X86TargetLowering()
|