Searched refs:RegType (Results 1 – 5 of 5) sorted by relevance
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
H A D | AArch64InstrFormats.td | 5641 [(set (AccumType RegType:$dst), 5642 (OpNode (AccumType RegType:$Rd), 5643 (InputType RegType:$Rn), 5663 [(set (AccumType RegType:$dst), 7894 …: BaseSIMDThreeSameVectorTied<Q, U, 0b010, 0b11111, RegType, asm, kind1, [(set (AccumType RegType:… 7917 RegType, RegType, V128, VectorIndexS, 7919 [(set (AccumType RegType:$dst), 8030 BaseSIMDIndexedTied<Q, U, 0b0, size, {0b111, Mixed}, RegType, RegType, V128, 8032 [(set (AccumType RegType:$dst), 8057 BaseSIMDIndexedTied<Q, U, 0, 0b10, opc, RegType, RegType, V128, [all …]
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H A D | AArch64FrameLowering.cpp | 2216 enum RegType { GPR, FPR64, FPR128, PPR, ZPR } Type; enum
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H A D | AArch64InstrInfo.td | 891 string rhs_kind, RegisterOperand RegType, 894 lhs_kind, rhs_kind, RegType, AccumType, 896 let Pattern = [(set (AccumType RegType:$dst), 897 (AccumType (int_aarch64_neon_usdot (AccumType RegType:$Rd), 901 (InputType RegType:$Rn))))];
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/netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
H A D | CodeGenPrepare.cpp | 6977 MVT RegType = TLI->getRegisterType(Context, TLI->getValueType(*DL, OldType)); in optimizeSwitchInst() local 6978 unsigned RegWidth = RegType.getSizeInBits(); in optimizeSwitchInst()
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/netbsd/external/apache2/llvm/dist/llvm/include/llvm/Target/ |
H A D | Target.td | 223 // RegType - Specify the list ValueType of the registers in this register
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