/netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
H A D | CallingConvLower.cpp | 254 for (MVT RegVT : RegParmTypes) { in analyzeMustTailForwardedRegisters() local 256 getRemainingRegParmsForType(RemainingRegs, RegVT, Fn); in analyzeMustTailForwardedRegisters() 258 const TargetRegisterClass *RC = TL->getRegClassFor(RegVT); in analyzeMustTailForwardedRegisters() 261 Forwards.push_back(ForwardedRegister(VReg, PReg, RegVT)); in analyzeMustTailForwardedRegisters()
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/BPF/ |
H A D | BPFISelLowering.cpp | 322 EVT RegVT = VA.getLocVT(); in LowerFormalArguments() local 323 MVT::SimpleValueType SimpleTy = RegVT.getSimpleVT().SimpleTy; in LowerFormalArguments() 327 << RegVT.getEVTString() << '\n'; in LowerFormalArguments() 335 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, RegVT); in LowerFormalArguments() 340 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue, in LowerFormalArguments() 343 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue, in LowerFormalArguments()
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/netbsd/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
H A D | SwitchLoweringUtils.h | 213 MVT RegVT; member 227 RegVT(RgVT), Emitted(E), ContiguousRange(CR), Parent(P), Default(D), in BitTestBlock()
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/AVR/ |
H A D | AVRISelLowering.cpp | 1149 EVT RegVT = VA.getLocVT(); in LowerFormalArguments() local 1151 if (RegVT == MVT::i8) { in LowerFormalArguments() 1153 } else if (RegVT == MVT::i16) { in LowerFormalArguments() 1160 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); in LowerFormalArguments() 1177 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, in LowerFormalArguments() 1182 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, in LowerFormalArguments() 1281 EVT RegVT = VA.getLocVT(); in LowerCall() local 1291 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, RegVT, Arg); in LowerCall() 1294 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, RegVT, Arg); in LowerCall() 1297 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, RegVT, Arg); in LowerCall() [all …]
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/ARC/ |
H A D | ARCISelLowering.cpp | 484 EVT RegVT = VA.getLocVT(); in LowerCallArguments() local 485 switch (RegVT.getSimpleVT().SimpleTy) { in LowerCallArguments() 488 << (unsigned)RegVT.getSimpleVT().SimpleTy << "\n"); in LowerCallArguments() 494 ArgIn = DAG.getCopyFromReg(Chain, dl, VReg, RegVT); in LowerCallArguments()
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/Lanai/ |
H A D | LanaiISelLowering.cpp | 460 EVT RegVT = VA.getLocVT(); in LowerCCCArguments() local 461 switch (RegVT.getSimpleVT().SimpleTy) { in LowerCCCArguments() 465 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, RegVT); in LowerCCCArguments() 471 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue, in LowerCCCArguments() 474 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue, in LowerCCCArguments() 485 << RegVT.getEVTString() << "\n"); in LowerCCCArguments()
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/MSP430/ |
H A D | MSP430ISelLowering.cpp | 642 EVT RegVT = VA.getLocVT(); in LowerCCCArguments() local 643 switch (RegVT.getSimpleVT().SimpleTy) { in LowerCCCArguments() 648 << RegVT.getEVTString() << "\n"; in LowerCCCArguments() 655 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, RegVT); in LowerCCCArguments() 661 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, in LowerCCCArguments() 664 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, in LowerCCCArguments()
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/M68k/ |
H A D | M68kISelLowering.cpp | 592 EVT RegVT = VA.getLocVT(); in LowerCall() local 603 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, RegVT, Arg); in LowerCall() 606 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, RegVT, Arg); in LowerCall() 609 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, RegVT, Arg); in LowerCall() 612 Arg = DAG.getBitcast(RegVT, Arg); in LowerCall() 893 EVT RegVT = VA.getLocVT(); in LowerFormalArguments() local 895 if (RegVT == MVT::i32) in LowerFormalArguments() 901 ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT); in LowerFormalArguments() 907 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue, in LowerFormalArguments() 910 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue, in LowerFormalArguments()
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLowering.cpp | 841 MVT RegVT = VA.getLocVT(); in LowerFormalArguments() local 843 RegVT = VA.getValVT(); in LowerFormalArguments() 845 const TargetRegisterClass *RC = getRegClassFor(RegVT); in LowerFormalArguments() 847 SDValue Copy = DAG.getCopyFromReg(Chain, dl, VReg, RegVT); in LowerFormalArguments() 853 assert(RegVT.getSizeInBits() <= 32); in LowerFormalArguments() 854 SDValue T = DAG.getNode(ISD::AND, dl, RegVT, in LowerFormalArguments() 855 Copy, DAG.getConstant(1, dl, RegVT)); in LowerFormalArguments() 856 Copy = DAG.getSetCC(dl, MVT::i1, T, DAG.getConstant(0, dl, RegVT), in LowerFormalArguments() 860 unsigned RegSize = RegVT.getSizeInBits(); in LowerFormalArguments() 862 Subtarget.isHVXVectorType(RegVT)); in LowerFormalArguments()
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/netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
H A D | CallLowering.cpp | 893 MVT RegVT = TLI->getRegisterTypeForCallingConv(Context, CallConv, VT); in getReturnInfo() local 894 Type *PartTy = EVT(RegVT).getTypeForEVT(Context); in getReturnInfo()
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H A D | IRTranslator.cpp | 1017 B.RegVT = getMVTForLLT(MaskTy); in emitBitTestHeader() 1049 LLT SwitchTy = getLLTForMVT(BB.RegVT); in emitBitTestCase()
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/XCore/ |
H A D | XCoreISelLowering.cpp | 1301 EVT RegVT = VA.getLocVT(); in LowerCCCArguments() local 1302 switch (RegVT.getSimpleVT().SimpleTy) { in LowerCCCArguments() 1307 << RegVT.getEVTString() << "\n"; in LowerCCCArguments() 1314 ArgIn = DAG.getCopyFromReg(Chain, dl, VReg, RegVT); in LowerCCCArguments()
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/netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
H A D | SelectionDAGBuilder.cpp | 2774 B.RegVT = VT.getSimpleVT(); in visitBitTestHeader() 2775 B.Reg = FuncInfo.CreateReg(B.RegVT); in visitBitTestHeader() 2813 MVT VT = BB.RegVT; in visitBitTestCase() 8232 const MVT RegVT = *TRI.legalclasstypes_begin(*RC); in GetRegistersForValue() local 8254 DAG.getNode(ISD::BITCAST, DL, RegVT, OpInfo.CallOperand); in GetRegistersForValue() 8255 OpInfo.ConstraintVT = RegVT; in GetRegistersForValue() 8276 ValueVT = RegVT; in GetRegistersForValue() 8305 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); in GetRegistersForValue() 8614 MVT RegVT = AsmNodeOperands[CurOp+1].getSimpleValueType(); in visitInlineAsm() local 10199 MVT RegVT = TLI->getRegisterType(*CurDAG->getContext(), VT); in LowerArguments() local [all …]
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H A D | TargetLowering.cpp | 7395 EVT RegVT = Value.getValueType(); in scalarizeVectorStore() local 7396 EVT RegSclVT = RegVT.getScalarType(); in scalarizeVectorStore() 7493 MVT RegVT = getRegisterType(*DAG.getContext(), intVT); in expandUnalignedLoad() local 7495 unsigned RegBytes = RegVT.getSizeInBits() / 8; in expandUnalignedLoad() 7499 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT); in expandUnalignedLoad() 7533 DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr, in expandUnalignedLoad() 7643 MVT RegVT = getRegisterType( in expandUnalignedStore() local 7648 unsigned RegBytes = RegVT.getSizeInBits() / 8; in expandUnalignedStore() 7652 SDValue StackPtr = DAG.CreateStackTemporary(StoreMemVT, RegVT); in expandUnalignedStore() 7671 RegVT, dl, Store, StackPtr, in expandUnalignedStore() [all …]
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H A D | LegalizeIntegerTypes.cpp | 1423 MVT RegVT = TLI.getRegisterType(*DAG.getContext(), VT); in PromoteIntRes_VAARG() local 1429 Parts[i] = DAG.getVAArg(RegVT, dl, Chain, Ptr, N->getOperand(2), in PromoteIntRes_VAARG() 1445 DAG.getConstant(i * RegVT.getSizeInBits(), dl, in PromoteIntRes_VAARG()
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
H A D | MipsISelLowering.cpp | 3664 MVT RegVT = VA.getLocVT(); in LowerFormalArguments() local 3666 const TargetRegisterClass *RC = getRegClassFor(RegVT); in LowerFormalArguments() 3671 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT); in LowerFormalArguments() 3677 if ((RegVT == MVT::i32 && ValVT == MVT::f32) || in LowerFormalArguments() 3678 (RegVT == MVT::i64 && ValVT == MVT::f64) || in LowerFormalArguments() 3679 (RegVT == MVT::f64 && ValVT == MVT::i64)) in LowerFormalArguments() 3681 else if (ABI.IsO32() && RegVT == MVT::i32 && in LowerFormalArguments() 3685 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, DL, Reg2, RegVT); in LowerFormalArguments()
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.cpp | 5363 const MVT RegVT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32; in prepareDescriptorIndirectCall() local 5367 SDValue LoadFuncPtr = DAG.getLoad(RegVT, dl, LDChain, Callee, MPI, in prepareDescriptorIndirectCall() 5373 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, RegVT, Callee, TOCOff); in prepareDescriptorIndirectCall() 5375 DAG.getLoad(RegVT, dl, LDChain, AddTOC, in prepareDescriptorIndirectCall() 5380 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, RegVT, Callee, PtrOff); in prepareDescriptorIndirectCall() 5382 DAG.getLoad(RegVT, dl, LDChain, AddPtr, in prepareDescriptorIndirectCall() 5415 const MVT RegVT = IsPPC64 ? MVT::i64 : MVT::i32; in buildCallOperands() local 5438 SDValue StackPtr = DAG.getRegister(StackPtrReg, RegVT); in buildCallOperands() 5448 RegVT)); in buildCallOperands() 6520 const MVT RegVT = IsPPC64 ? MVT::i64 : MVT::i32; in CC_AIX() local [all …]
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H A D | PPCISelDAGToDAG.cpp | 700 EVT RegVT = ST->getValue().getValueType(); in tryTLSXFormStore() local 707 Opcode = (RegVT == MVT::i32) ? PPC::STBXTLS_32 : PPC::STBXTLS; in tryTLSXFormStore() 711 Opcode = (RegVT == MVT::i32) ? PPC::STHXTLS_32 : PPC::STHXTLS; in tryTLSXFormStore() 715 Opcode = (RegVT == MVT::i32) ? PPC::STWXTLS_32 : PPC::STWXTLS; in tryTLSXFormStore() 745 EVT RegVT = LD->getValueType(0); in tryTLSXFormLoad() local 751 Opcode = (RegVT == MVT::i32) ? PPC::LBZXTLS_32 : PPC::LBZXTLS; in tryTLSXFormLoad() 755 Opcode = (RegVT == MVT::i32) ? PPC::LHZXTLS_32 : PPC::LHZXTLS; in tryTLSXFormLoad() 759 Opcode = (RegVT == MVT::i32) ? PPC::LWZXTLS_32 : PPC::LWZXTLS; in tryTLSXFormLoad()
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
H A D | X86ISelLowering.cpp | 3658 EVT RegVT = VA.getLocVT(); in LowerFormalArguments() local 3670 if (RegVT == MVT::i8) in LowerFormalArguments() 3672 else if (RegVT == MVT::i16) in LowerFormalArguments() 3674 else if (RegVT == MVT::i32) in LowerFormalArguments() 3678 else if (RegVT == MVT::f32) in LowerFormalArguments() 3680 else if (RegVT == MVT::f64) in LowerFormalArguments() 3682 else if (RegVT == MVT::f80) in LowerFormalArguments() 3684 else if (RegVT == MVT::f128) in LowerFormalArguments() 4082 EVT RegVT = VA.getLocVT(); in LowerCall() local 24302 assert(RegVT.isInteger() && in LowerLoad() [all …]
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.cpp | 4884 EVT RegVT = VA.getLocVT(); in LowerFormalArguments() local 4887 if (RegVT == MVT::i32) in LowerFormalArguments() 4889 else if (RegVT == MVT::i64) in LowerFormalArguments() 4891 else if (RegVT == MVT::f16 || RegVT == MVT::bf16) in LowerFormalArguments() 4893 else if (RegVT == MVT::f32) in LowerFormalArguments() 4895 else if (RegVT == MVT::f64 || RegVT.is64BitVector()) in LowerFormalArguments() 4897 else if (RegVT == MVT::f128 || RegVT.is128BitVector()) in LowerFormalArguments() 4899 else if (RegVT.isScalableVector() && in LowerFormalArguments() 4900 RegVT.getVectorElementType() == MVT::i1) in LowerFormalArguments() 4902 else if (RegVT.isScalableVector()) in LowerFormalArguments() [all …]
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.cpp | 2871 EVT RegVT = VA.getLocVT(); in IsEligibleForTailCallOptimization() local 2876 if (VA.needsCustom() && (RegVT == MVT::f64 || RegVT == MVT::v2f64)) { in IsEligibleForTailCallOptimization() 2885 if (RegVT == MVT::v2f64) { in IsEligibleForTailCallOptimization() 4318 EVT RegVT = VA.getLocVT(); in LowerFormalArguments() local 4346 if (RegVT == MVT::f16 || RegVT == MVT::bf16) in LowerFormalArguments() 4348 else if (RegVT == MVT::f32) in LowerFormalArguments() 4350 else if (RegVT == MVT::f64 || RegVT == MVT::v4f16 || in LowerFormalArguments() 4351 RegVT == MVT::v4bf16) in LowerFormalArguments() 4353 else if (RegVT == MVT::v2f64 || RegVT == MVT::v8f16 || in LowerFormalArguments() 4354 RegVT == MVT::v8bf16) in LowerFormalArguments() [all …]
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