/netbsd/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
H A D | ARMInstrVFP.td | 2003 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), 2027 (VMLAS SPR:$dstin, SPR:$a, SPR:$b)>, 2044 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), 2068 (VMLSS SPR:$dstin, SPR:$a, SPR:$b)>, 2084 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), 2136 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), 2177 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), 2201 (VFMAS SPR:$dstin, SPR:$a, SPR:$b)>, 2229 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), 2281 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), [all …]
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H A D | ARMInstrCDE.td | 487 def cde_vcx_s_regs : CDE_VCX_RegisterOperandsTemplate<SPR>; 551 (f32 (CDE_VCX1A_fpsp p_imm:$coproc, SPR:$acc, imm_11b:$imm))>; 557 def : Pat<(f32 (int_arm_cde_vcx2 timm:$coproc, (f32 SPR:$n), timm:$imm)), 558 (f32 (CDE_VCX2_fpsp p_imm:$coproc, SPR:$n, imm_6b:$imm))>; 559 def : Pat<(f32 (int_arm_cde_vcx2a timm:$coproc, (f32 SPR:$acc), (f32 SPR:$n), 561 (f32 (CDE_VCX2A_fpsp p_imm:$coproc, SPR:$acc, SPR:$n, imm_6b:$imm))>; 568 def : Pat<(f32 (int_arm_cde_vcx3 timm:$coproc, (f32 SPR:$n), (f32 SPR:$m), 570 (f32 (CDE_VCX3_fpsp p_imm:$coproc, (f32 SPR:$n), (f32 SPR:$m), 572 def : Pat<(f32 (int_arm_cde_vcx3a timm:$coproc, (f32 SPR:$acc), (f32 SPR:$n), 573 (f32 SPR:$m), timm:$imm)), [all …]
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H A D | ARMRegisterInfo.td | 398 def SPR : RegisterClass<"ARM", [f32], 32, (sequence "S%u", 0, 31)> { 399 let AltOrders = [(add (decimate SPR, 2), SPR), 400 (add (decimate SPR, 4), 401 (decimate SPR, 2), 402 (decimate (rotl SPR, 1), 4), 403 (decimate (rotl SPR, 1), 2))]; 411 let AltOrders = [(add (decimate HPR, 2), SPR), 422 // Subset of SPR which can be used as a source of NEON scalars for 16-bit 447 def FPWithVPR : RegisterClass<"ARM", [f32], 32, (add SPR, DPR, VPR)> { 452 // 32-bit SPR subregs). [all …]
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H A D | ARMRegisterBanks.td | 13 def FPRRegBank : RegisterBank<"FPRB", [HPR, SPR, DPR, QPR]>;
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/netbsd/external/gpl3/gdb/dist/sim/ppc/ |
H A D | dc-complex | 42 ## Move to/from SPR instructions - LR=8 is munged into 0x100 == 256 44 #array,boolean: 11:20:11:20:SPR: 0xfc0007ff:0x7c0003a6:256 45 #array,boolean: 11:20:11:20:SPR: 0xfc0007ff:0x7c0002a6:256 52 ## Move to/from SPR instructions - separate out LR case 54 # Move to SPR 55 array,boolean: 11:20:11:20:SPR: 0xfc0007ff:0x7c0003a6:256 56 # Move from SPR 57 array,boolean: 11:20:11:20:SPR: 0xfc0007ff:0x7c0002a6:256
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H A D | dc-stupid | 42 ## Move to/from SPR instructions - LR=8 is munged into 0x100 == 256 44 #array,boolean: 11:20:11:20:SPR: 0xfc0007ff:0x7c0003a6:256 45 #array,boolean: 11:20:11:20:SPR: 0xfc0007ff:0x7c0002a6:256 52 ## Move to/from SPR instructions - separate out LR case 54 # Move to SPR 55 #array,boolean: 11:20:11:20:SPR: 0xfc0007ff:0x7c0003a6:256 56 # Move from SPR 57 #array,boolean: 11:20:11:20:SPR: 0xfc0007ff:0x7c0002a6:256
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H A D | idecode_fields.h | 68 #define SPR_5_9_ (SPR & 0x1f) 69 #define SPR_0_4_ (SPR >> 5) 70 #define SPR_0_ ((SPR & BIT10(0)) != 0)
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H A D | BUGS | 122 "mtlr %RS":SPR.something 123 "mtspr %SPR, %RS"
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/netbsd/external/gpl3/gdb.old/dist/sim/ppc/ |
H A D | dc-complex | 42 ## Move to/from SPR instructions - LR=8 is munged into 0x100 == 256 44 #array,boolean: 11:20:11:20:SPR: 0xfc0007ff:0x7c0003a6:256 45 #array,boolean: 11:20:11:20:SPR: 0xfc0007ff:0x7c0002a6:256 52 ## Move to/from SPR instructions - separate out LR case 54 # Move to SPR 55 array,boolean: 11:20:11:20:SPR: 0xfc0007ff:0x7c0003a6:256 56 # Move from SPR 57 array,boolean: 11:20:11:20:SPR: 0xfc0007ff:0x7c0002a6:256
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H A D | dc-stupid | 42 ## Move to/from SPR instructions - LR=8 is munged into 0x100 == 256 44 #array,boolean: 11:20:11:20:SPR: 0xfc0007ff:0x7c0003a6:256 45 #array,boolean: 11:20:11:20:SPR: 0xfc0007ff:0x7c0002a6:256 52 ## Move to/from SPR instructions - separate out LR case 54 # Move to SPR 55 #array,boolean: 11:20:11:20:SPR: 0xfc0007ff:0x7c0003a6:256 56 # Move from SPR 57 #array,boolean: 11:20:11:20:SPR: 0xfc0007ff:0x7c0002a6:256
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H A D | idecode_fields.h | 68 #define SPR_5_9_ (SPR & 0x1f) 69 #define SPR_0_4_ (SPR >> 5) 70 #define SPR_0_ ((SPR & BIT10(0)) != 0)
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H A D | BUGS | 122 "mtlr %RS":SPR.something 123 "mtspr %SPR, %RS"
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/netbsd/external/gpl3/gdb/dist/gdb/testsuite/gdb.ada/bias/ |
H A D | bias.adb | 38 SPR : Some_Packed_Record := (R => -4, S => -5); variable 50 Do_Nothing (SPR'Address);
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/netbsd/external/gpl3/gdb.old/dist/gdb/testsuite/gdb.ada/bias/ |
H A D | bias.adb | 38 SPR : Some_Packed_Record := (R => -4, S => -5); variable 50 Do_Nothing (SPR'Address);
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/netbsd/external/gpl3/gdb/dist/cpu/ |
H A D | or1kcommon.cpu | 88 (or (sll UWI (enum UWI (.sym "SPR-GROUP-" spr-group)) spr-shift) 89 (enum UWI (.sym "SPR-INDEX-" spr-group "-" spr-index)))) 206 SPR-GROUP- 260 SPR-INDEX- 340 "SPR field msb positions" 342 SPR-FIELD-MSB- 356 "SPR field lsb positions" 358 SPR-FIELD-SIZE- 372 "SPR field masks" 374 SPR-FIELD-MASK-
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/netbsd/external/gpl3/binutils/dist/cpu/ |
H A D | or1kcommon.cpu | 88 (or (sll UWI (enum UWI (.sym "SPR-GROUP-" spr-group)) spr-shift) 89 (enum UWI (.sym "SPR-INDEX-" spr-group "-" spr-index)))) 206 SPR-GROUP- 260 SPR-INDEX- 340 "SPR field msb positions" 342 SPR-FIELD-MSB- 356 "SPR field lsb positions" 358 SPR-FIELD-SIZE- 372 "SPR field masks" 374 SPR-FIELD-MASK-
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/netbsd/external/gpl3/gdb.old/dist/cpu/ |
H A D | or1kcommon.cpu | 88 (or (sll UWI (enum UWI (.sym "SPR-GROUP-" spr-group)) spr-shift) 89 (enum UWI (.sym "SPR-INDEX-" spr-group "-" spr-index)))) 206 SPR-GROUP- 260 SPR-INDEX- 340 "SPR field msb positions" 342 SPR-FIELD-MSB- 356 "SPR field lsb positions" 358 SPR-FIELD-SIZE- 372 "SPR field masks" 374 SPR-FIELD-MASK-
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/netbsd/external/gpl3/binutils.old/dist/cpu/ |
H A D | or1kcommon.cpu | 88 (or (sll UWI (enum UWI (.sym "SPR-GROUP-" spr-group)) spr-shift) 89 (enum UWI (.sym "SPR-INDEX-" spr-group "-" spr-index)))) 220 SPR-GROUP- 274 SPR-INDEX- 354 "SPR field msb positions" 356 SPR-FIELD-MSB- 370 "SPR field lsb positions" 372 SPR-FIELD-SIZE- 386 "SPR field masks" 388 SPR-FIELD-MASK-
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
H A D | PPCRegisterInfo.td | 51 // SPR - One of the 32-bit special-purpose registers 52 class SPR<bits<10> num, string n> : PPCReg<n> { 247 def LR : SPR<8, "lr">, DwarfRegNum<[-2, 65]>; 249 def LR8 : SPR<8, "lr">, DwarfRegNum<[65, -2]>; 252 def CTR : SPR<9, "ctr">, DwarfRegNum<[-2, 66]>; 253 def CTR8 : SPR<9, "ctr">, DwarfRegNum<[66, -2]>; 256 def VRSAVE: SPR<256, "vrsave">, DwarfRegNum<[109]>; 262 def SPEFSCR: SPR<512, "spefscr">, DwarfRegNum<[612, 112]>; 264 def XER: SPR<1, "xer">, DwarfRegNum<[76]>; 267 // (which really is SPR register 1); this is the only bit interesting to a [all …]
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/netbsd/external/gpl3/gdb/dist/include/opcode/ |
H A D | spu-insns.h | 149 APUOP(M_MFSPR, RR, 0x00c, "mfspr", _A2(A_T,A_S), 00002, SPR) /* MFSPR RT<-SA */ 150 APUOP(M_RDCH, RR, 0x00d, "rdch", _A2(A_T,A_H), 00002, SPR) /* ReaDCHannel RT<-CA:data */ 151 APUOP(M_RCHCNT, RR, 0x00f, "rchcnt", _A2(A_T,A_H), 00002, SPR) /* ReaDCHanCouNT RT<-CA:count */ 160 APUOP(M_MTSPR, RR, 0x10c, "mtspr", _A2(A_S,A_T), 00001, SPR) /* MTSPR SA<-RT */ 161 APUOP(M_WRCH, RR, 0x10d, "wrch", _A2(A_H,A_T), 00001, SPR) /* ChanWRite CA<-RT */ 335 APUOP(M_SYSCALL, RI7, 0x10c, "syscall", _A3(A_T,A_A,A_S7N), 00002, SPR) /* System Ca…
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/netbsd/external/gpl3/binutils.old/dist/include/opcode/ |
H A D | spu-insns.h | 149 APUOP(M_MFSPR, RR, 0x00c, "mfspr", _A2(A_T,A_S), 00002, SPR) /* MFSPR RT<-SA */ 150 APUOP(M_RDCH, RR, 0x00d, "rdch", _A2(A_T,A_H), 00002, SPR) /* ReaDCHannel RT<-CA:data */ 151 APUOP(M_RCHCNT, RR, 0x00f, "rchcnt", _A2(A_T,A_H), 00002, SPR) /* ReaDCHanCouNT RT<-CA:count */ 160 APUOP(M_MTSPR, RR, 0x10c, "mtspr", _A2(A_S,A_T), 00001, SPR) /* MTSPR SA<-RT */ 161 APUOP(M_WRCH, RR, 0x10d, "wrch", _A2(A_H,A_T), 00001, SPR) /* ChanWRite CA<-RT */ 335 APUOP(M_SYSCALL, RI7, 0x10c, "syscall", _A3(A_T,A_A,A_S7N), 00002, SPR) /* System Ca…
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/netbsd/external/gpl3/binutils/dist/include/opcode/ |
H A D | spu-insns.h | 149 APUOP(M_MFSPR, RR, 0x00c, "mfspr", _A2(A_T,A_S), 00002, SPR) /* MFSPR RT<-SA */ 150 APUOP(M_RDCH, RR, 0x00d, "rdch", _A2(A_T,A_H), 00002, SPR) /* ReaDCHannel RT<-CA:data */ 151 APUOP(M_RCHCNT, RR, 0x00f, "rchcnt", _A2(A_T,A_H), 00002, SPR) /* ReaDCHanCouNT RT<-CA:count */ 160 APUOP(M_MTSPR, RR, 0x10c, "mtspr", _A2(A_S,A_T), 00001, SPR) /* MTSPR SA<-RT */ 161 APUOP(M_WRCH, RR, 0x10d, "wrch", _A2(A_H,A_T), 00001, SPR) /* ChanWRite CA<-RT */ 335 APUOP(M_SYSCALL, RI7, 0x10c, "syscall", _A3(A_T,A_A,A_S7N), 00002, SPR) /* System Ca…
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/netbsd/external/gpl3/gdb.old/dist/include/opcode/ |
H A D | spu-insns.h | 149 APUOP(M_MFSPR, RR, 0x00c, "mfspr", _A2(A_T,A_S), 00002, SPR) /* MFSPR RT<-SA */ 150 APUOP(M_RDCH, RR, 0x00d, "rdch", _A2(A_T,A_H), 00002, SPR) /* ReaDCHannel RT<-CA:data */ 151 APUOP(M_RCHCNT, RR, 0x00f, "rchcnt", _A2(A_T,A_H), 00002, SPR) /* ReaDCHanCouNT RT<-CA:count */ 160 APUOP(M_MTSPR, RR, 0x10c, "mtspr", _A2(A_S,A_T), 00001, SPR) /* MTSPR SA<-RT */ 161 APUOP(M_WRCH, RR, 0x10d, "wrch", _A2(A_H,A_T), 00001, SPR) /* ChanWRite CA<-RT */ 335 APUOP(M_SYSCALL, RI7, 0x10c, "syscall", _A3(A_T,A_A,A_S7N), 00002, SPR) /* System Ca…
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/netbsd/external/gpl3/gdb/dist/sim/testsuite/sim/frv/ |
H A D | testutils.inc | 69 ; Set GR with SPR 159 ; Set SPR with immediate value 175 ; increment SPR with immediate value 453 ori gr28,1,gr28 ; Turn on SPR.ET 455 andi gr28,0xfffffffe,gr28 ; Turn off SPR.ET
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/netbsd/external/gpl3/gdb.old/dist/sim/testsuite/sim/frv/ |
H A D | testutils.inc | 69 ; Set GR with SPR 159 ; Set SPR with immediate value 175 ; increment SPR with immediate value 453 ori gr28,1,gr28 ; Turn on SPR.ET 455 andi gr28,0xfffffffe,gr28 ; Turn off SPR.ET
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