Searched refs:Spills (Results 1 – 6 of 6) sorted by relevance
| /netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | LiveInterval.cpp | 1155 OS << ' ' << Spills[I]; in print()
1235 if (!Spills.empty() && coalescable(Spills.back(), Seg)) { in add()
1236 Seg.start = Spills.back().start; in add()
1237 Seg.end = std::max(Spills.back().end, Seg.end); in add()
1238 Spills.pop_back(); in add()
1258 Spills.push_back(Seg); in add()
1269 LiveRange::iterator SpillSrc = Spills.end(); in mergeSpills()
1283 Spills.erase(SpillSrc, Spills.end()); in mergeSpills()
1295 if (Spills.empty()) { in flush()
1303 if (GapSize < Spills.size()) { in flush()
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| H A D | InlineSpiller.cpp | 123 SmallPtrSet<MachineInstr *, 16> &Spills,
128 MachineBasicBlock *Root, SmallPtrSet<MachineInstr *, 16> &Spills,
135 SmallPtrSet<MachineInstr *, 16> &Spills,
1275 SmallPtrSet<MachineInstr *, 16> &Spills, in rmRedundantSpills() argument
1281 for (const auto CurrentSpill : Spills) { in rmRedundantSpills()
1297 Spills.erase(SpillToRm); in rmRedundantSpills()
1307 MachineBasicBlock *Root, SmallPtrSet<MachineInstr *, 16> &Spills, in getVisitOrders() argument
1330 for (const auto Spill : Spills) { in getVisitOrders()
1392 SmallPtrSet<MachineInstr *, 16> &Spills, in runHoistSpills() argument
1406 rmRedundantSpills(Spills, SpillsToRm, SpillBBToSpill); in runHoistSpills()
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| H A D | RegAllocGreedy.cpp | 555 unsigned Spills = 0; member
565 return !(Reloads || FoldedReloads || Spills || FoldedSpills || in isEmpty()
573 Spills += other.Spills; in add()
3150 if (Spills) { in report()
3151 R << NV("NumSpills", Spills) << " spills "; in report()
3207 ++Stats.Spills; in computeStats()
3248 Stats.SpillsCost = RelFreq * Stats.Spills; in computeStats()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Transforms/Coroutines/ |
| H A D | CoroFrame.cpp | 321 SpillInfo Spills; member
328 for (const auto &P : Spills) in getAllDefs()
393 for (const auto &E : Spills) { in dumpSpills()
554 for (auto &S : Spills) in updateLayoutIndex()
1139 for (auto &S : FrameData.Spills) { in buildFrameType()
1922 for (const auto &E : Spills) { in rewriteMaterializableInstructions()
2579 SpillInfo Spills; in buildCoroutineFrame() local
2593 Spills[&I].push_back(DVI); in buildCoroutineFrame()
2596 if (Spills.empty()) in buildCoroutineFrame()
2603 Spills.clear(); in buildCoroutineFrame()
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| /netbsd/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | LiveInterval.h | 933 SmallVector<LiveRange::Segment, 16> Spills; variable
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstructions.td | 614 // that switch the VGPR indexing mode. Spills to accvgprs could be effected by
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