/netbsd/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
H A D | HexagonPatterns.td | 373 def Sub: pf2<sub>; def Or: pf2<or>; def Srl: pf2<srl>; 1077 def: OpR_RI_pat<S2_lsr_i_r, Srl, i32, I32, u5_0ImmPred>; 1080 def: OpR_RI_pat<S2_lsr_i_p, Srl, i64, I64, u6_0ImmPred>; 1083 def: OpR_RI_pat<S2_lsr_i_vh, Srl, v4i16, V4I16, u4_0ImmPred>; 1086 def: OpR_RI_pat<S2_lsr_i_vh, Srl, v2i32, V2I32, u5_0ImmPred>; 1090 def: OpR_RR_pat<S2_lsr_r_r, Srl, i32, I32, I32>; 1093 def: OpR_RR_pat<S2_lsr_r_p, Srl, i64, I64, I32>; 1253 def: AccRRR_pat<S2_lsr_r_r_acc, Add, Su<Srl>, I32, I32, I32>; 1254 def: AccRRR_pat<S2_lsr_r_r_nac, Sub, Su<Srl>, I32, I32, I32>; 1255 def: AccRRR_pat<S2_lsr_r_r_and, And, Su<Srl>, I32, I32, I32>; [all …]
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUISelDAGToDAG.cpp | 332 SDValue Srl = In.getOperand(0); in isExtractHiElt() local 333 if (Srl.getOpcode() == ISD::SRL) { in isExtractHiElt() 334 if (ConstantSDNode *ShiftAmt = dyn_cast<ConstantSDNode>(Srl.getOperand(1))) { in isExtractHiElt() 336 Out = stripBitcast(Srl.getOperand(0)); in isExtractHiElt() 2165 const SDValue &Srl = N->getOperand(0); in SelectS_BFE() local 2166 ConstantSDNode *Shift = dyn_cast<ConstantSDNode>(Srl.getOperand(1)); in SelectS_BFE() 2177 Srl.getOperand(0), ShiftVal, WidthVal)); in SelectS_BFE()
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H A D | SIISelLowering.cpp | 10232 SDValue Srl = DAG.getNode(ISD::SRL, SL, MVT::i32, Elt, in performExtractVectorEltCombine() local 10234 DCI.AddToWorklist(Srl.getNode()); in performExtractVectorEltCombine() 10236 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SL, EltVT.changeTypeToInteger(), Srl); in performExtractVectorEltCombine()
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
H A D | ARMISelDAGToDAG.cpp | 447 SDValue Srl = N1.getOperand(0); in PreprocessISelDAG() local 449 if (!isOpcWithIntImmediate(Srl.getNode(), ISD::SRL, Srl_imm) || in PreprocessISelDAG() 468 Srl = CurDAG->getNode(ISD::SRL, SDLoc(Srl), MVT::i32, in PreprocessISelDAG() 469 Srl.getOperand(0), in PreprocessISelDAG() 470 CurDAG->getConstant(Srl_imm + TZ, SDLoc(Srl), in PreprocessISelDAG() 473 Srl, in PreprocessISelDAG() 474 CurDAG->getConstant(And_imm, SDLoc(Srl), MVT::i32)); in PreprocessISelDAG() 476 N1, CurDAG->getConstant(TZ, SDLoc(Srl), MVT::i32)); in PreprocessISelDAG()
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/netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
H A D | DAGCombiner.cpp | 4219 SDValue Srl = DAG.getNode(ISD::SRL, DL, VT, Sign, Inexact); in visitSDIVLike() local 4220 AddToWorklist(Srl.getNode()); in visitSDIVLike() 4221 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N0, Srl); in visitSDIVLike() 5550 SDValue Srl = Not.getOperand(0); in combineShiftAnd1ToBitTest() local 5551 if (Srl.getOpcode() == ISD::TRUNCATE) in combineShiftAnd1ToBitTest() 5552 Srl = Srl.getOperand(0); in combineShiftAnd1ToBitTest() 5555 if (Srl.getOpcode() != ISD::SRL || !Srl.hasOneUse() || in combineShiftAnd1ToBitTest() 5556 !isa<ConstantSDNode>(Srl.getOperand(1))) in combineShiftAnd1ToBitTest() 5562 const APInt &ShiftAmt = Srl.getConstantOperandAPInt(1); in combineShiftAnd1ToBitTest() 5570 SDValue X = DAG.getZExtOrTrunc(Srl.getOperand(0), DL, VT); in combineShiftAnd1ToBitTest()
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
H A D | X86ISelDAGToDAG.cpp | 1854 SDValue Srl = DAG.getNode(ISD::SRL, DL, VT, X, Eight); in foldMaskAndShiftToExtract() local 1855 SDValue And = DAG.getNode(ISD::AND, DL, VT, Srl, NewMask); in foldMaskAndShiftToExtract() 1865 insertDAGNode(DAG, N, Srl); in foldMaskAndShiftToExtract()
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/netbsd/share/misc/ |
H A D | domains | 261 .cipriani Hotel Cipriani Srl
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/netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
H A D | LegalizerHelper.cpp | 5812 auto Srl = MIRBuilder.buildLShr(DstTy, R, ExponentSub); in lowerFPTOSI() local 5818 R = MIRBuilder.buildSelect(DstTy, CmpGt, Shl, Srl); in lowerFPTOSI()
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